Cell Modeling & Verification Engineer - RTL/Verilog Expert

NVIDIA AI; Santa Clara (CA); On-site; USD 100,000 - 190,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA's VLSI team is seeking a Cell Modeling and Verification Engineer to help develop ASICs and verify designs on new NVIDIA hardware. You will work with Verilog, SystemVerilog, and scripting to model, verify, and prototype mixed-signal cells, ensuring performance and power targets.

Ideal candidates have a background in electrical/computer engineering, hands-on RTL simulation, and strong Verilog knowledge, plus Python or Perl scripting abilities.

Qualifications

• Bachelor's or Master's degree in Electrical/Computer Engineering (or equivalent).
• Hands-on experience with RTL simulation and waveform debug.
• Strong understanding of Verilog HDL.
• Scripting experience with Python or Perl.
• Knowledge of fundamental digital design concepts.

Responsibilities

• Develop behavioral model and verification for custom mixed-signal design cells used across NVIDIA products.
• Model, verify, and prototype mixed-signal designs using Verilog/SystemVerilog, Python, or Perl.
• Collaborate with library build, cell integration, ASIC verification and DFT simulation teams.
• Document and deliver fully verified RTL to meet design targets.

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Verilog

SystemVerilog

Job description

NVIDIA's VLSI team is seeking a Cell Modeling and Verification Engineer to help develop ASICs and verify designs on new NVIDIA hardware. You will work with Verilog, SystemVerilog, and scripting to model, verify, and prototype mixed-signal cells, ensuring performance and power targets.

Ideal candidates have a background in electrical/computer engineering, hands-on RTL simulation, and strong Verilog knowledge, plus Python or Perl scripting abilities.