Cell Modeling and Verification Engineer - New College Grad 2026

NVIDIA Gruppe; Santa Clara (CA); On-site; USD 100,000 - 166,750; Full time

Job summary

NVIDIA Gruppe is seeking a talented engineer to develop behavioral models and verification for mixed signal designs used in NVIDIA products. The role requires a strong background in Verilog HDL and scripting skills in Python or Perl.

Applicants should have a Bachelor's or Master's degree in Electrical or Computer Engineering, along with hands-on experience in RTL simulation or waveform debug. The base salary ranges from 100,000 USD to 189,750 USD depending on levels and qualifications.

Qualifications

• Hands-on experience with RTL simulation and waveform debug.
• Strong understanding of Verilog HDL.
• Scripting experience and skills using Python or Perl.
• Knowledge of fundamental digital design and logic design concepts.

Responsibilities

• Develop behavioral model and verification for custom mixed signal design cells.
• Collaborate with cross-function teams regarding library build and ASIC verification.
• Deliver fully verified and high-performance RTL to achieve design targets.

Skills

Verilog HDL

RTL simulation

Python

Perl

Digital design concepts

Education

Bachelors or Masters in Electrical Engineering or Computer Engineering

Job description

What you will be doing

• Work with sophisticated technologies and develop behavioral model and verification for custom mixed signal design cells that would be used on all the NVIDIA products.
• Use Verilog, SystemVerilog, Perl, or Python and understanding of PLL and other high-speed interconnects to model, verify, emulate/prototype mixed‑signal designs.
• Collaborate with cross‑function teams with regards to library build, cell integration, ASIC verification and DFT simulation.
• Document, implement, and deliver fully verified and high‑performance RTL to achieve design targets.

What we need to see

• Bachelors or Masters in Electrical Engineering or Computer Engineering (or equivalent experience).
• Hands‑on experience with RTL simulation and waveform debug.
• Strong understanding of Verilog HDL.
• Scripting experience and skills using Python or Perl.
• Knowledge of fundamental digital design and logic design concepts.

Ways to stand out from the crowd

• Previous digital design experience is a plus.
• Previous experience running simulations in Verilog.
• Shown ability to collaborate with many groups and communicate technical details.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 100,000 USD - 166,750 USD for Level 1, and 116,000 USD - 189,750 USD for Level 2. You will also be eligible for equity and benefits.

Applications for this job will be accepted until April 5, 2026.

Equal Opportunity Employer

NVIDIA is committed to fostering a diverse work environment and is proud to be an equal opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law.