Avionics FPGA Verification Engineer - Clearance Eligible

Game 7 Staffing; Costa Mesa (CA); On-site; USD 90,000 - 120,000; Full time

Job summary

Game 7 Staffing in Costa Mesa, CA is seeking an FPGA/ASIC verification engineer to architect UVM verification environments for AMD FPGA/SoC designs in flight-critical avionics. You will develop verification plans traceable to requirements and author SystemVerilog Assertions for compliance checks.

The role requires 2+ years of production verification, experience with Questa, VCS, Xcelium or Vivado simulators, Git workflows, and eligibility for a U.S. Secret clearance.

Qualifications

• Master’s degree in Electrical or Computer Engineering (Preferred).
• 2+ years FPGA/ASIC verification experience in production.
• Proficient in SystemVerilog, UVM, and SVA in production.
• Experience with industry simulators (Questa, VCS, Xcelium, or Vivado) in production.
• Git-based workflows including code review in production.
• Eligible for U.S. Secret security clearance.

Responsibilities

• Architect UVM verification environments for AMD FPGA/SoC designs.
• Develop verification plans with traceability to requirements.
• Author SystemVerilog Assertions for compliance checks.
• Build functional coverage models and drive code coverage analysis.
• Develop constrained-random test sequences for corner-case bugs.
• Debug failures using waveform tools and simulation logs.
• Collaborate on RTL reviews and bug resolution.
• Support hardware validation and board bring-up.
• Author verification closure reports and coverage summaries.

Skills

SystemVerilog

UVM methodology

SVA

FPGA/ASIC verification

Git workflows

Security clearance eligibility

Education

Master’s degree in Electrical or Computer Engineering

Tools

Questa

VCS

Xcelium

Vivado

Job description

Game 7 Staffing in Costa Mesa, CA is seeking an FPGA/ASIC verification engineer to architect UVM verification environments for AMD FPGA/SoC designs in flight-critical avionics. You will develop verification plans traceable to requirements and author SystemVerilog Assertions for compliance checks.

The role requires 2+ years of production verification, experience with Questa, VCS, Xcelium or Vivado simulators, Git workflows, and eligibility for a U.S. Secret clearance.