Automotive ASIC Front-End Synthesis/STA & DFT Engineer

AXONNE; San Jose (CA); On-site; USD 160,000 - 190,000; Full time

Job summary

Axonne Inc. is a Silicon Valley startup shaping automotive in-vehicle semiconductor solutions. We seek an experienced ASIC Front-End Design Engineer to own the RTL-to-gates flow, with a strong focus on synthesis, STA, DFT, and MBIST integration.

You will hand off a timing-constrained, DFT-ready gate-level netlist to backend PD, collaborating closely to achieve timing closure. Backend P&R is not in scope. You will build and maintain the end-to-end flow, write robust constraints, and drive

Qualifications

• Bachelor's or Master's degree in Electrical/Computer Engineering or related field.
• 5+ years of hands-on ASIC front-end flows with strong depth in synthesis and STA.
• Proficiency with industry-standard synthesis and STA tools.
• Ability to build a synthesis/DFT flow from scratch.
• Strong command of SDC constraints and multi-corner/multi-mode analysis.
• Hands-on experience with scan insertion and ATPG tools.
• Memory BIST insertion experience.
• Strong scripting for flow automation.

Responsibilities

• Own logic synthesis of RTL designs to gate-level netlists with timing, area, and power closure.
• Develop and maintain SDC constraints across modes and corners.
• Build, script, and automate the synthesis and DFT flow.
• Collaborate with backend PD to align constraints and handoff netlists.
• Implement scan chain insertion and ATPG pattern generation.
• Insert and configure memory BIST for embedded memories.
• Debug DFT issues during ATPG, simulation, or silicon bring-up.
• Review test coverage reports and drive closure.
• Maintain flow documentation and drive automation improvements.

Skills

Synthesis & STA

DFT Insertion

Scripting (Tcl/Python)

Flow Automation

Constraint Debugging

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Synopsys Design Compiler / Fusion Compiler

Cadence Genus

Synopsys PrimeTime

Synopsys DFTMAX

Tessent Scan/FastScan

Modus

Cadence Memory BIST

Job description

Axonne Inc. is a Silicon Valley startup shaping automotive in-vehicle semiconductor solutions. We seek an experienced ASIC Front-End Design Engineer to own the RTL-to-gates flow, with a strong focus on synthesis, STA, DFT, and MBIST integration.

You will hand off a timing-constrained, DFT-ready gate-level netlist to backend PD, collaborating closely to achieve timing closure. Backend P&R is not in scope. You will build and maintain the end-to-end flow, write robust constraints, and drive