ASIC Verification Engineer — UVM, SystemVerilog, SoC (Onsite Allentown)

Experis Technology Group

Allentown (Lehigh County)

On-site

USD 66,000 - 94,000

Full time

5 days ago
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Benefits offered by this job

Medical and Prescription Drug Plans
Dental Plan
Vision Plan
401(k), Plus Match
Weekly Pay

Job summary

Experis Technology Group's client is seeking an ASIC Verification Engineer in Allentown, Pennsylvania onsite to support next-generation SoC designs.

You will develop UVM-based verification environments, create verification plans, and lead debug efforts with cross-functional teams to ensure design testability.

The role combines strong SystemVerilog skills with timing, gate-level simulation, and firmware delivery using C.

Qualifications

  • Bachelor's degree in Electrical Engineering or related field.
  • Experience in ASIC or SOC verification with UVM based testbench development.
  • Proficiency in SystemVerilog and verification methodologies from block level to system level.
  • Experience in identifying and resolving complex design and verification issues.
  • Timing and gate level simulation experience, along with C coding for firmware delivery for post silicon bringup.

Responsibilities

  • Develop and implement Universal Verification Methodology (UVM) based verification environments.
  • Create comprehensive verification plans at both block and system levels.
  • Design and implement verification components including assertions, traffic generators, agents, and scoreboards.
  • Collaborate with cross-functional teams to evaluate design testability and verification requirements.
  • Lead debug efforts and provide solutions for complex technical challenges.

Skills

UVM verification
SystemVerilog
Firmware C coding
Debugging complex issues
Timing analysis

Education

Bachelor's degree in Electrical Engineering

Job description

Experis Technology Group's client is seeking an ASIC Verification Engineer in Allentown, Pennsylvania onsite to support next-generation SoC designs.

You will develop UVM-based verification environments, create verification plans, and lead debug efforts with cross-functional teams to ensure design testability.

The role combines strong SystemVerilog skills with timing, gate-level simulation, and firmware delivery using C.

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