ASIC Engineer - Early Career: Space-Flight Verilog Innovator

Blue Origin; United States; Vor Ort; USD 129.000 - 180.000; Vollzeit

Benefits dieser Stelle

Medical, dental, vision

Stock options

Paid time off

Education support

Zusammenfassung

Blue Origin seeks engineers to contribute to Verilog/SystemVerilog design and verification for digital blocks within large-scale SoCs. You will work with senior engineers to implement test plans, coverage, and debugging in a collaborative team focused on safety and reliability.

Ideal candidates have coursework or project experience in RTL design, digital logic, and basic verification concepts, and are eager to grow in a fast-paced aerospace environment that values innovation and impact.

Qualifikationen

• BS or MS in Electrical Engineering, Computer Engineering, or related technical field (completed or in final year).
• Coursework or project experience with Verilog/SystemVerilog RTL design or verification.
• Understanding of digital logic design fundamentals (combinational/sequential logic, FSMs, timing).
• Familiarity with basic verification concepts (testbenches, simulation, coverage).
• Strong problem-solving skills and attention to detail.
• Effective communication and ability to work in a collaborative team environment.

Aufgaben

• Contribute to Verilog/SystemVerilog design and verification of digital blocks within larger SoCs.
• Support module-level and subsystem-level verification using SystemVerilog/UVM.
• Write test plans and functional coverage definitions under guidance from senior team members.
• Assist with CDC/RDC/LINT checks and clean-up.
• Participate in code coverage and functional coverage closure activities.
• Help develop assertions, protocol monitors, and scoreboards for testbenches.
• Support integration and verification of external IP (e.g., bus fabrics, standard interfaces).
• Learn and apply industry-standard verification methodologies (UVM, formal verification basics).
• Debug RTL and testbench issues with guidance from senior engineers.
• Document design intent, verification results, and test coverage.

Kenntnisse

Verilog/SystemVerilog RTL

Digital logic fundamentals

SystemVerilog/UVM

Debugging and problem-solving

Communication in a team

Ausbildung

BS or MS in Electrical Engineering/Computer Engineering

Tools

EDA tools (VCS, Xcelium, Questa)

Jobbeschreibung

Blue Origin seeks engineers to contribute to Verilog/SystemVerilog design and verification for digital blocks within large-scale SoCs. You will work with senior engineers to implement test plans, coverage, and debugging in a collaborative team focused on safety and reliability.

Ideal candidates have coursework or project experience in RTL design, digital logic, and basic verification concepts, and are eager to grow in a fast-paced aerospace environment that values innovation and impact.