ASIC Verification Engineer: Memory Mgmt (New Grad)

NVIDIA Corporation; Northern (KY); Hybrid; USD 100,000 - 167,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation is hiring a Verification Engineer for Memory Management as a New College Graduate. You will verify the Memory Management Unit of the world's leading GPUs, building testbenches, BFMs, checkers and monitors while collaborating with architects and software teams across sites.

The role emphasizes SystemVerilog and C/C++, constrained random testing with coverage, and debugging using industry tools. On-site opportunities exist across multiple US locations.

Qualifications

• Pursuing or recently completed a BS/MS in Electrical Engineering, Computer Science, Computer Engineering or related field.
• Exposure to computer architecture, ASIC design and verification methodology.
• Strong proficiency with SystemVerilog, C and/or C++, test planning, coverage closure, and creating reusable verification components.
• Knowledgeable in constrained random testing with functional coverage and assertion-based verification.
• Understanding of object oriented programming concepts.
• Exposure to simulation tools like VCS, IES and debug tools like Debussy, GDB.

Responsibilities

• Verify Memory Management Unit designs for GPUs; develop verification infrastructure including testbenches, BFMs, checkers, monitors.
• Collaborate with architects, designers and software engineers across sites to achieve goals.
• Plan and drive methodology direction for testbench with advanced methodologies.

Skills

SystemVerilog

C/C++

test planning

coverage closure

UVM

debugging

debug tools

Education

BS/MS in Electrical Engineering / Computer Science / Computer Engineering

Tools

VCS

IES

Debussy

GDB

Job description

NVIDIA Corporation is hiring a Verification Engineer for Memory Management as a New College Graduate. You will verify the Memory Management Unit of the world's leading GPUs, building testbenches, BFMs, checkers and monitors while collaborating with architects and software teams across sites.

The role emphasizes SystemVerilog and C/C++, constrained random testing with coverage, and debugging using industry tools. On-site opportunities exist across multiple US locations.