ASIC Verification Engineer

Links Technology Solutions, Inc.; Carlsbad (CA); Hybrid; USD 96,000 - 110,000; Full time

Benefits offered by this job

Health insurance

Vision & dental

401K

Job summary

Links Technology Solutions, Inc. in Carlsbad, CA onsite/hybrid is seeking an ASIC Verification Engineer to develop UVM-based verification environments for next‑generation SoC designs.

You will create verification plans, build components like assertions and scoreboards, and work across teams to ensure testability and successful silicon bring‑up. Ideal candidates have 5–12 years of industry experience, expertise in SystemVerilog, C and Python, and familiarity with formal verification techniques.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• UVM-based testbench development experience.
• Experience in ASIC or SOC verification and test-plan delivery.

Responsibilities

• Develop and implement UVM-based verification environments.
• Create verification plans at block and system levels.
• Lead debug and collaborate to meet verification requirements.

Skills

UVM testbench

SystemVerilog

C programming

Python scripting

Education

Bachelor's degree in Electrical Engineering

Tools

RTL simulators

C/C++ toolchain

Job description

## ASIC Verification Engineer**Carlsbad,CA92009**Posted: 11/05/2026Industry: DEVJob Number: 1259Pay Rate: $70-$80 / hrRemote Work Available?: Onsite## Job Description**Title: ASIC VERIFICATION ENGINEER** **Location:** Carlsbad, CA onsite/hybrid **Pay Rate:** $70-$80/HR **Duration:** 1 yr extendable **Summary:** Join our client's innovative team developing next-generation silicon solutions for a major network manufacturer. We are seeking a collaborative Design Verification Engineer with 5-12 years of industry experience to help create cutting edge System-on-Chip (SoC) designs delivered first time right. You will work in a collaborative environment, participating in architectural decisions and verification strategies that directly impact product success. Our team values diverse perspectives and creative problem-solving approaches to deliver exceptional customer experiences. **Description – ASIC Verification Engineer*** Develop and implement Universal Verification Methodology (UVM) based verification environments.* Create comprehensive verification plans at both block and system levels.* Design and implement verification components including assertions, traffic generators, agents, and scoreboards.* Collaborate with cross-functional teams to evaluate design testability and verification requirements.* Lead debug efforts and provide solutions for complex technical challenges.**Qualifications – ASIC Verification Engineer*** Bachelor's degree in Electrical Engineering or a related field.* UVM Based testbench development.* Experience in ASIC or SOC verification.* Demonstrated experience in developing test plans and verification infrastructure.* Practical knowledge of verification methodologies from block level to system level.* Proficiency in System Verilog.* Experience in identifying and resolving complex design and verification issues.* Timing and gate level simulation experience.* C coding for firmware delivery for post silicon bringup.* Bachelors/master's degree in electrical or communications engineering or a related field.* Experience with formal verification techniques including abstraction and end-to-end checking.* Experience with industry-standard tools and scripting languages (Python or Perl) for automation.* System Verilog coding and debug.* AI based CAD efficiency improvisation initiatives.* High speed serial protocols preferred UCIe, PCIE.* Analog debug experience including DAC/ADC & calibrations white-box verification.**Benefits:*** $70-$80/hr* Available health, life, vision, and dental insurance* 401K Matching#IND2## Meet Your Recruiter## Thomas Kretz VP of Talent & ServicesTalent and professional services manager with 20+ years of progressive experience in the staffing industry.