Senior ASIC Verification Engineer - High-Speed PHY

Broadcom; San Jose (CA); In loco; USD 101.000 - 162.000; Tempo pieno

Vantaggi offerti da questo lavoro

Medical, dental and vision plans

401(K) participation including company

Employee Stock Purchase Program (ESPP)

Employee Assistance Program (EAP)

Paid holidays

Paid sick leave and vacation time

Descrizione del lavoro

Broadcom is seeking a capable engineer to verify high-speed interconnect ASICs. Responsibilities include developing verification environments using SystemVerilog UVM, understanding IEEE Ethernet protocols, and collaborating across architecture, firmware, and layout teams through full product development cycle.

Candidates should have a BS in Engineering with 5+ years' related experience, or a MS/PhD; proficiency in HDL (Verilog/SystemVerilog/VHDL), C/C++, and scripting (Python/Perl/Tcl) is

Competenze

• Bachelor's in Engineering with 5+ years of related experience, or Master/PhD in Engineering.
• Design/verification experience or equivalent.
• Proficient in HDL languages (Verilog/SystemVerilog/VHDL).
• C/C++ programming experience; scripting skills (Python/PERL/TCL) are a plus.

Mansioni

• Develop understanding of IEEE Ethernet protocols.
• Understand chip architecture and design specifications.
• Create verification environment and testbenches in SystemVerilog UVM.
• Contribute to block and chip level verification tasks.
• Develop scripts and tools to improve efficiency and quality.

Conoscenze

Self-motivated

Good communicator

Team player

Fast learner

Formazione

Bachelor's in Engineering

Master or PhD in Engineering

Strumenti

HDL Verilog/SystemVerilog/VHDL

C/C++

Python

PERL

TCL

Descrizione del lavoro

Broadcom is seeking a capable engineer to verify high-speed interconnect ASICs. Responsibilities include developing verification environments using SystemVerilog UVM, understanding IEEE Ethernet protocols, and collaborating across architecture, firmware, and layout teams through full product development cycle.

Candidates should have a BS in Engineering with 5+ years' related experience, or a MS/PhD; proficiency in HDL (Verilog/SystemVerilog/VHDL), C/C++, and scripting (Python/Perl/Tcl) is