ASIC Verification Engineer – High-Speed Interconnect

Broadcom Inc.; Irvine (CA); On-site; USD 101,000 - 162,000; Full time

Benefits offered by this job

Medical plans

Dental plans

Vision plans

401K with match

ESPP

EAP

Paid holidays

Sick leave

Vacation time

Job summary

Broadcom Inc. is seeking an ASIC Verification Engineer for the HSIP Group.

The role focuses on verification of high-speed interconnect PHYs from 100Gbps to 400Gbps, collaborating with cross-functional teams across marketing, architecture, firmware, physical and layout to drive product development from definition to production. The candidate combines formal training in engineering with hands-on experience in SystemVerilog UVM environments, HDL proficiency, and scripting to improve test

Qualifications

• Bachelor's in Engineering with 5+ years of related experience, or a Master’s with 3+ years, or PhD with no experience.
• HDL languages proficiency required (Verilog/SystemVerilog/VHDL).
• C/C++ programming proficiency is a must, with OO experience a plus.
• Scripting in Python, PERL, or TCL is a plus.

Responsibilities

• Develop verification environment and testbench components in SystemVerilog UVM.
• Perform block-level and chip-level verification tasks.
• Understand chip architecture, microarchitecture and design specifications.
• Develop scripts and tools to improve efficiency and quality of work.
• Collaborate with marketing, architecture, firmware, physical and layout teams.

Skills

Ethernet protocols

SystemVerilog UVM

HDL languages

C/C++

Scripting languages

Team player

Education

Bachelor's in Engineering

Master's in Engineering

PhD (with no experience)

Tools

Verilog/SystemVerilog

VHDL

Job description

Broadcom Inc. is seeking an ASIC Verification Engineer for the HSIP Group.

The role focuses on verification of high-speed interconnect PHYs from 100Gbps to 400Gbps, collaborating with cross-functional teams across marketing, architecture, firmware, physical and layout to drive product development from definition to production. The candidate combines formal training in engineering with hands-on experience in SystemVerilog UVM environments, HDL proficiency, and scripting to improve test