ASIC Verification Engineer (UVM & GLS Focus)

Amiseq Inc.; United States; On-site; USD 120,000 - 180,000; Full time

Job summary

Amiseq Inc. seeks an experienced ASIC/SoC verification engineer to lead end-to-end verification efforts. The candidate will build and maintain UVM environments from scratch, develop robust testbenches, and drive coverage closure across complex designs in a fast-paced setting.

The role emphasizes strong SystemVerilog/UVM skills, GLS experience, and ability to collaborate with design and customer teams to ensure high-quality verification results.

Qualifications

• 6-10+ years of ASIC/SoC verification experience.
• Proven experience building complete UVM verification environments from scratch.
• UVM and GLS experience.
• Functional coverage, assertions, and regression experience.
• Experience with industry-standard simulators: VCS, Xcelium, Questa.

Responsibilities

• Own verification of complex ASIC/SoC design blocks from planning through sign-off.
• Develop UVM verification environments from scratch including testbench, agents, drivers, monitors, and coverage models.
• Drive functional verification with directed and constrained-random methods and achieve coverage closure.
• Execute and debug Gate-Level Simulations (GLS) including timing and reset issues.
• Perform deep waveform analysis, root-cause debugging, regression triage, and sign-off activities.
• Collaborate with design, architecture, and customer teams to ensure verification quality.

Skills

UVM

SystemVerilog

GLS

Functional Coverage

Debugging

Tools

Synopsys VCS

Cadence Xcelium

Siemens Questa

Job description

• Strong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.


• Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock synchronization issues, power-up sequence validation, and debug of post-synthesis/post-layout simulation failures.


• Expert-level proficiency in SystemVerilog and UVM for complex ASIC/SoC verification.


• Protocol knowledge in Ethernet, PCIe, or UCIe is preferred but secondary to strong UVM and GLS expertise.

Key Responsibilities

• Own verification of complex ASIC/SoC design blocks from planning through sign-off.


• Develop and maintain UVM-based verification environments from scratch, including testbench infrastructure, agents, drivers, monitors, scoreboards, sequences, and coverage models.


• Drive functional verification using directed and constrained-random methodologies and achieve coverage closure.


• Execute and debug Gate-Level Simulations (GLS), including timing-related failures, SDF-annotated simulations, reset issues, X-propagation, and initialization/debug challenges.


• Perform deep waveform analysis, root-cause debugging, regression triage, and verification sign-off activities.


• Collaborate with design, architecture, and customer teams to ensure comprehensive verification coverage and quality.

Required Qualifications

• 6-10+ years of ASIC/SoC Verification experience.


• Proven experience building complete UVM verification environments from scratch.


• UVM


• Gate-Level Simulation (GLS)


• Functional Coverage


• Assertions


• Experience with industry-standard simulators such as Synopsys VCS, Cadence Xcelium, or Siemens Questa.


• Strong debugging skills involving waveform analysis, protocol debugging, and root-cause identification.