ASIC Implementation & Low-Power Design Engineer

AGL Technologies Inc.; City of Utica (NY); On-site; USD 120,000 - 180,000; Full time

Job summary

AGL Technologies Inc. in Utica, NY is seeking a senior digital ASIC design engineer to own low-power methodology and block-level implementation across a 12nm tape-out flow. You will integrate CPF/UPF power intent with power-rail analysis and drive CDC/STA tasks for IP blocks.

You will collaborate with top-level architects to ensure robust power-domain isolation, correct level-shifter usage, and efficient timing closure, while supporting ECOs and sign-off for physical design.

Qualifications

• US citizenship is required due to defense program work.
• 5+ years of hands-on digital ASIC design, synthesis, and low-power sign-off experience.
• Proven expertise with power intent formats (CPF or UPF/IEEE 1801), power gating, multi-VDD, retention strategies, and isolation logic.
• Direct experience with FinFET nodes (12nm or below preferred).
• Deep experience with industry-standard synthesis (Genus), STA (Tempus), and power/rail analysis tools (Voltus).
• Solid background in SystemVerilog/Verilog/VHDL, Tcl scripting for flow automation, and timing constraints (SDC).

Responsibilities

• Take ownership of low-power methodology, integrating CPF/UPF and low-power checks into the EDA toolchain.
• Perform static and dynamic IR drop analysis, EM checks, and power-domain/clock-gating optimization on 12nm silicon.
• Drive synthesis, timing constraints, STA, and CDC analysis for digital IP blocks using existing floorplans.
• Collaborate with top-level leads to ensure power-domain isolation, level-shifter insertion, retention registers, and power-state sequencing.
• Provide ECO and sign-off support, ensuring timing closure and power sign-off for block-level handoffs to physical design.

Skills

Digital ASIC design

Low-power design

SystemVerilog/Verilog/VHDL

Tcl scripting

Tools

Genus

Tempus

Voltus

Conformal Low Power

Job description

In this dual-impact role, you will take ownership of our low-power design methodology, enhancing and tightly integrating our power intent (CPF/UPF) and rail analysis flows into our existing 12nm tape-out pipeline. Additionally, you will take ownership of block-level digital implementation (synthesis, STA, CDC) for a suite of established IP blocks, freeing technical leadership to focus on top-level system architecture.

Key responsibilities

• Low-power methodology & flow enhancement: Review, harden, and fully integrate our power intent specifications (CPF/UPF) and static low-power check flows (e.g., Conformal Low Power) into the main EDA toolchain.
• Power & rail analysis: Perform static and dynamic IR drop analysis, electromigration (EM) checks, and power domain/clock-gating optimization on 12nm silicon.
• Block implementation ownership: Drive synthesis, timing constraints definition, static timing analysis (STA), and CDC analysis for several assigned digital IP blocks using existing floorplans.
• Top-level power integration: Work closely with top-level leads to ensure clean power domain isolation, level-shifter insertion, retention registers, and power-state sequencing.
• ECO & sign-off support: Perform timing closure and power sign-off checks for block-level handoffs to physical design.

Required qualifications

• Citizenship requirement: Due to the nature of our defense programs, US citizenship is required.
• Experience: 5+ years of hands-on digital ASIC design, synthesis, and low-power sign-off experience.
• Low-power standards: Proven expertise with power intent formats (CPF or UPF/IEEE 1801), power gating, multi-VDD, retention strategies, and isolation logic.
• Advanced process nodes: Direct experience working in FinFET nodes (12nm or below preferred).
• EDA toolchain proficiency: Deep experience with industry-standard synthesis (Genus), STA (Tempus), and power/rail analysis tools (Voltus).
• Implementation skills: Solid background in SystemVerilog/Verilog/VHDL, Tcl scripting for flow automation, and timing constraints (SDC).