ASIC/FPGA Verification Engineer – UVM Expert

New York Life Insurance; Seattle (WA); On-site; USD 120,000 - 170,000; Full time

Benefits offered by this job

Relocation assistance

Job summary

New York Life Insurance in Seattle seeks an Associate ASIC-FPGA Verification Engineer to support multiple product lines in commercial and defense electronics development. You will use architectural docs to implement test bench functions, develop SystemVerilog models, and create scripts and Makefiles for verification work.

The ideal candidate has 6–9 years of digital ASIC/FPGA verification, deep UVM knowledge, and proven experience building self-checking test benches for SoCs/FPGA.

Qualifications

• Bachelor’s or master’s degree in engineering, computer science, mathematics, physics or chemistry.
• 6 to 9 years of experience in digital ASIC/FPGA verification.
• In‑depth experience writing UVM sequences, virtual sequences, drivers, monitors, predictors and scoreboards.
• Experience building self‑checking simulation test benches from scratch for SoCs/ASIC/FPGA.
• Experience working with internal and external VIPs and evaluating multiple vendors.
• Strong knowledge of SystemVerilog and verification concepts.
• Proficiency with Linux/Unix terminal commands and scripting languages (Make, Perl, Python, shell).
• Experience using revision control systems (SVN, CVS, Git).

Responsibilities

• Use high‑level architectural documentation and algorithm descriptions to implement functions for test bench architecture and design.
• Develop SystemVerilog models to verify design implementation and create scripts and Makefiles.
• Lead analysis of customer and system requirements, developing architectural approaches and detailed specifications for electronic products.
• Lead reviews of testing and analysis activities to ensure compliance with requirements.
• Identify, track and report technical performance measures to track progress and ensure compliance.
• Support functional verification, simulation, emulation, safety and other technical services and methodologies.
• Create verification plan IPs and subsystems.
• Coordinate engineering support throughout product lifecycle.
• Plan research projects to develop concepts for future product designs.
• Work under minimal direction.

Skills

SystemVerilog

UVM

Test bench development

SoC/ASIC/FPGA verification

VIPs

Scripting

Education

Bachelor’s or master’s degree in engineering, computer science, mathematics, physics or chemistry

Tools

Git

Make

Perl

Python

Shell

Job description

New York Life Insurance in Seattle seeks an Associate ASIC-FPGA Verification Engineer to support multiple product lines in commercial and defense electronics development. You will use architectural docs to implement test bench functions, develop SystemVerilog models, and create scripts and Makefiles for verification work.

The ideal candidate has 6–9 years of digital ASIC/FPGA verification, deep UVM knowledge, and proven experience building self-checking test benches for SoCs/FPGA.