ASIC/FPGA Verification Engineer - Contract

Boeing Future of Flight; Mountain View (CA); On-site; USD 104,697 - 111,585; Full time

Benefits offered by this job

Medical

Dental

Vision

401K

Job summary

Tundra Technical Solutions in Mountain View, CA is seeking an Electrical Design and Analysis Engineer (Contract) to verify ASICs and FPGAs using SystemVerilog and UVM. The role is on-site, for a one-year contract.

The ideal candidate has a BS in EE/CE/CS, experience with testbench development, and familiarity with coverage metrics. The job involves using Python/Perl for flows, supporting FPGA bring-up, and collaborating across design teams.

Qualifications

• Bachelor’s degree in EE, CE, CS, or related field required.
• Experience with ASIC/FPGA verification using SystemVerilog and UVM.
• Ability to build self-checking testbenches and use object-oriented SV features.
• Familiarity with functional coverage and code coverage closure.
• Comfortable in Linux and using scripting tools.

Responsibilities

• Write SystemVerilog/UVM testbenches to verify ASICs and FPGAs.
• Develop self-checking, reusable UVM components: drivers, monitors, scoreboards, sequencers.
• Build functional coverage models and close code coverage gaps.
• Create tests that verify DSP and third-party IP integration.
• Run simulations, linting, CDC checks, static timing checks, and gate-level regressions.
• Use scripting (Python/Perl/Make) and revision control (git/svn) to automate flows.
• Support FPGA bring-up, hardware emulation/prototyping, and hardware integration tests.
• Collaborate with system and hardware teams to capture requirements and debug issues.

Skills

SystemVerilog

UVM verification

Testbench development

Linux scripting

Code coverage

Education

Bachelor’s degree in EE/CE/CS or related field

Tools

Palladium emulators

FPGA prototyping

Git/SVN

Job description

Tundra Technical Solutions in Mountain View, CA is seeking an Electrical Design and Analysis Engineer (Contract) to verify ASICs and FPGAs using SystemVerilog and UVM. The role is on-site, for a one-year contract.

The ideal candidate has a BS in EE/CE/CS, experience with testbench development, and familiarity with coverage metrics. The job involves using Python/Perl for flows, supporting FPGA bring-up, and collaborating across design teams.