ASIC Engineer, Implementation – CAD

Anysilicon; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Meta is seeking an ASIC Implementation Engineer to join the Infrastructure Silicon team in Austin, TX. The role focuses on custom silicon development for data center applications, crafting CAD methodologies and automation scripts to support RTL to physical design signoff.

You will collaborate across engineering teams to ensure efficient tape-outs of next-generation infrastructure chips. You will design and maintain production CAD platforms and web-based design tools for silicon exploration,

Qualifications

• 2 years of experience in synthesis and physical design.
• Proficiency in Python for algorithm development and automation.
• Experience in developing CAD/EDA tools and engineering automation.
• Knowledge of RTL synthesis, physical design, and PPA optimization.
• Experience collaborating with cross-functional teams to resolve timing, area, and power issues.

Responsibilities

• Design, develop, and maintain production CAD platforms and web-based design tools for silicon exploration.
• Build data models, algorithms, and Python APIs for large-scale design data.
• Develop tooling for SOC floorplans and facilitate early floorplan exploration and area estimation to connect architecture with implementation.
• Create debugging features for logical and physical connectivity analysis on DEF and netlist data, optimizing timing and area.
• Automate methodologies across all front-end tools and collaborate with design, DV, architecture, and physical design engineers for effective handoffs and feedback.

Skills

Python scripting

Cross-functional teamwork

Synthesis knowledge

Tools

CAD/EDA tooling

Verilog/DEF/LEF parsing

Web-based design tools

Job description

Meta is looking for an ASIC Implementation Engineer to join the Infrastructure Silicon team, focusing on custom silicon development for data center applications. The role involves developing CAD methodologies and automation scripts to support ASIC implementation from RTL to physical design signoff, collaborating with various engineering teams to ensure efficient tape-outs of next-generation infrastructure chips.

Responsibilities:

• Design, develop, and maintain production‑level CAD platforms and web‑based design tools for silicon architecture exploration and engineering analysis.
• Build optimized data models, algorithms, and Python APIs for large‑scale design data, achieving significant runtime improvements over native EDA solutions.
• Develop tooling for generating SOC floorplans and facilitate early floorplan exploration and area estimation to connect architecture with implementation.
• Create debug features for logical and physical connectivity analysis on DEF and netlist data, optimizing timing and area.
• Automate methodologies across all front‑end tools and collaborate with design, DV, architecture, and physical design engineers for effective handoffs and feedback.

Qualifications:

• 2 years of experience in synthesis and physical design.
• Proficiency in Python for algorithm development and automation.
• Experience in developing CAD/EDA tools and engineering automation.
• Knowledge of RTL synthesis, physical design, and PPA optimization.
• Experience working with cross‑functional teams to resolve timing, area, and power issues.

Skills:

• Experience with DEF, netlists, and floorplanning data.
• Strong software engineering fundamentals including data structures and algorithms.
• Knowledge of multi‑chiplet connectivity and 2.5D/3D SoIC assembly.
• Experience writing parsers for design formats like Verilog netlist and LEF/DEF.
• Ability to build web‑based engineering applications with interactive visualization frameworks.