ASIC Engineer: Digital/Analog IP Design + RSU/Bonus

QUALCOMM, Inc.; San Diego (CA); On-site; USD 101,000 - 152,000; Full time

Benefits offered by this job

Annual discretionary bonus

RSU grants

Competitive benefits package

Job summary

Qualcomm Technologies, Inc. is seeking an ASIC Engineer in San Diego to define, model, design (digital/analog), optimize and verify IP for high-performance, low-power products. You will document results and collaborate with cross-functional teams to meet system requirements.

The role emphasizes hands-on architecture, circuit specifications, and implementation strategies, with opportunities to work across RTL to GDS flows and design verification methods.

Qualifications

• Bachelor's degree in Science, Engineering, or related field required.
• Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science preferred.
• 6+ months of experience with architecture and design tools.
• 6+ months of experience with scripting tools and programming languages.
• 6+ months of experience with design verification methods.

Responsibilities

• Applies ASIC knowledge to define, model, design, optimize, verify, validate, and document IP for high-performance, low-power products.
• Assists in creating architectures, circuit specs, logic designs, and system simulations from requirements.
• Collaborates on implementation strategies meeting system and customer needs.
• Supports process flow evaluation from high-level design to place-and-route, timing, and verification.

Skills

ASIC design knowledge

RTL design

Scripting languages

Design verification methods

Education

Bachelor's degree in Science/Engineering

Master's degree in EE/CE/CS

Tools

RTL to GDS Flow

Virtuoso

Job description

Qualcomm Technologies, Inc. is seeking an ASIC Engineer in San Diego to define, model, design (digital/analog), optimize and verify IP for high-performance, low-power products. You will document results and collaborate with cross-functional teams to meet system requirements.

The role emphasizes hands-on architecture, circuit specifications, and implementation strategies, with opportunities to work across RTL to GDS flows and design verification methods.