ASIC Design & Verification Engineer

Nokia; Sunnyvale (CA); On-site; USD 100,000 - 160,000; Full time

Job summary

Nokia is seeking a skilled Design Verification Engineer for their Sunnyvale location. The role focuses on verifying complex processor designs, ensuring product quality through automation in Python and C/C++. Candidates should have strong expertise in SystemVerilog, UVM, and familiarity with critical memory and networking protocols.

Qualifications

• Knowledge of industry-standard verification environments and frameworks.
• Experience with simulation tools and methodologies including coverage analysis and debugging.
• Familiarity with PCIe, Ethernet protocols, and verification of these subsystems.

Responsibilities

• Develop and execute verification environments for processor and memory designs.
• Create and maintain test benches to ensure comprehensive functional coverage.
• Collaborate with cross-functional teams to address verification challenges.

Skills

Verification using SystemVerilog

UVM

Strong programming skills in Python

Strong programming skills in C/C++

Knowledge of PCIe protocols

Knowledge of Ethernet protocols

Tools

Simulation tools

Version control systems (Git)

Job description

Applied R&D (AR) consists of target-oriented research either with the goal of solving a particular problem / answering a specific question or for multi-discipline design, development, and implementation of hardware, software, and systems including maintenance support. Supplies techno-economic consulting to clients. AR work is characterised by its detailed and complex nature in order to systematically combine existing knowledge and practices to further developing and incrementally improving products, operational processes, and customer-specific feature development.

Integration, Verification & Testing (IVT) comprises the integration of SW and / or HW or system components into system, platform, product releases, or networks and verifies the integrated entity or network against particular requirements and specifications. Covers setup and maintenance of laboratory and associated equipment, tools, and devices.

Qualifications

Required Qualifications:

• Knowledge of industry-standard verification environments and frameworks.
• Verification using SystemVerilog and UVM in complex digital designs.
• Experience with simulation tools and methodologies, including coverage analysis, debugging, and performance evaluation.
• Strong programming skills in Python and C/C++ to support verification automation and system-level testing.
• Familiarity with PCIe, Ethernet protocols, and verification of these subsystems.

Other Preferred Qualifications:

• Experience with other verification methodologies or tools such as formal verification, emulation, or hardware-based verification platforms.
• Familiarity with advanced processor architectures, multi-core designs, and interconnect systems.
• In-depth knowledge of high-performance memory systems, including HBM.
• Experience with version control systems such as Git.

Responsibilities

Seeking an experienced and motivated Design Verification Engineer to join our team, located in the SF Bay Area. In this role, you will be responsible for verifying complex processor designs, memory subsystems, and cache controllers, ensuring high-quality products that meet performance, power, and functional requirements. The ideal candidate will have expertise in SystemVerilog (SV), UVM, and strong programming skills in Python, C/C++. Familiarity with memory technologies such as HBM, and industry-standard interfaces like PCIe and Ethernet will be highly beneficial.

Key Responsibilities:

• Develop, implement, and execute verification environments for processor designs, memory subsystems, and cache controllers using SystemVerilog and UVM.
• Create and maintain test benches to ensure comprehensive coverage of functional requirements, performance specifications, and corner cases.
• Work closely with design engineers to understand design specifications and use that knowledge to create effective and efficient test plans and verification strategies.
• Develop and execute complex simulation-based verification tasks and analyze results to identify design bugs and ensure high-quality product delivery.
• Leverage Python and C/C++ to support automation, scripting, and integration with verification flows.
• Collaborate with cross-functional teams to address verification challenges and implement performance optimizations.
• Apply your knowledge of HBM, PCIe, and Ethernet interfaces to verify these key subsystems in real-world scenarios.
• Identify areas of improvement in the verification process and contribute to the development of methodologies for better productivity and coverage.
• Document and communicate verification results, metrics, and progress to senior engineers and project managers.

Other Required Qualifications:

• Knowledge of industry-standard verification environments and frameworks.
• Verification using SystemVerilog and UVM in complex digital designs.
• Experience with simulation tools and methodologies, including coverage analysis, debugging, and performance evaluation.
• Strong programming skills in Python and C/C++ to support verification automation and system-level testing.
• Familiarity with PCIe, Ethernet protocols, and verification of these subsystems.

Other Preferred Qualifications:

• Experience with other verification methodologies or tools such as formal verification, emulation, or hardware-based verification platforms.
• Familiarity with advanced processor architectures, multi-core designs, and interconnect systems.
• In-depth knowledge of high-performance memory systems, including HBM.
• Experience with version control systems such as Git.