ASIC Design Verification Engineer

Davita Inc.; San Jose (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

A leading technology company is seeking an ASIC Design Verification Engineer to join their Silicon One development team in San Jose, CA. The role involves collaborating with cross-functional teams to verify ASICs through simulation and emulation. Candidates should have a strong background in SystemVerilog and UVM methodology, along with experience in building testbenches and verifying complex designs. The company promotes a diverse and inclusive culture, encouraging personal growth and community involvement.

Qualifications

• 5+ years experience with Bachelor's or 3+ years with Master's.
• Experience verifying complex blocks and SoC designs.

Responsibilities

• Maintain and enhance existing DV environments.
• Construct testbenches for new blocks.
• Develop test plans and drive verification closure.

Skills

SystemVerilog

UVM methodology

Scripting skills

Debugging

Education

Bachelor's degree

Master's degree

Tools

Perl

Python

Job description

The application window is expected to close on 6/3/2025.

This is an onsite role and requires working out of the Milpitas/San Jose office location.

Who We Are:

The Common Hardware Group (CHG) delivers silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design networking hardware for Enterprises, Service Providers, the Public Sector, and Non-Profit Organizations worldwide. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market, enabling deployment from Top of Rack (TOR) switches to web-scale data centers, across service providers, enterprise networks, and data centers with a unified routing and switching portfolio. Join us to help shape Cisco's innovative solutions by designing, developing, and testing complex ASICs.

Who You'll Work With:

You will be part of the Silicon One development team as an ASIC design verification engineer in San Jose, CA. You will collaborate with verification engineers, designers, hardware, and cross-functional teams to verify ASICs through simulation, emulation, and ASIC bring-up processes.

What You'll Do:

• Maintain and enhance existing DV environments.
• Construct testbenches, including scoreboards, agents, sequencers, and monitors for new blocks.
• Develop test plans, create test cases, debug regression failures, and drive verification closure.
• Ensure comprehensive verification coverage through code and functional coverage reviews.

Minimum Qualifications:

• Bachelor's degree with 5+ years or Master's degree with 3+ years of relevant experience; experience with SystemVerilog and UVM methodology.
• Experience verifying complex blocks, clusters, and top-level SoC designs.
• Hands-on experience building testbenches from scratch, using SystemVerilog constraints, structures, and classes.
• Knowledge of functional coverage and constrained random DV environments.
• Scripting skills in Perl and/or Python.

Preferred Qualifications:

• Strong domain knowledge in protocols such as PCIe, CXL, Ethernet, AHB/AXI, DDR, MMU.
• Experience with Veloce/HAPS is a plus.
• Knowledge of formal verification tools (iev/vc formal) is a plus.

#WeAreCisco

We celebrate diverse skills and perspectives, aiming to power an inclusive future. Our culture encourages learning, development, and hybrid work, fostering community and belonging through initiatives like Inclusive Communities and paid volunteer time. Our purpose is to lead in technology that powers the internet, supporting customers in reimagining applications, securing enterprises, transforming infrastructure, and achieving sustainability. Join us and be your authentic self!