ASIC Design Verification Engineer (all levels)

SQL Pager LLC; San Francisco, Sunnyvale (CA, CA); On-site; USD 120,000 - 180,000; Full time

Job summary

A leading technology company is seeking an ASIC Design Verification Engineer to optimize low latency SoCs for critical applications. The ideal candidate will have extensive experience in design verification, UVM, and a strong background in programming. In this role, you will contribute to groundbreaking technology that enhances real-time performance while working within a collaborative and innovative team environment.

Benefits

Medical insurance

Vision insurance

Dental insurance

401(k)

Qualifications

• Minimum of 10+ years of design verification experience for Principal role.
• Experience in developing a complete chip-level UVM test bench from scratch.
• Expertise in coverage driven System Verilog UVM.

Responsibilities

• Architect and build a UVM verification environment for SoC-level.
• Collaborate with teams to verify SoC features.
• Construct chip level test plans and develop test vectors.

Skills

Design Verification

System Verilog UVM

C/C++

Python

Multi-CPU Environment

Debugging

Education

BSEE/BSCE

Master in Science

Job description

ASIC Design Verification Engineer

Client Overview
Our client is building the first latency optimized SoC for their industry. Using its proven AI accelerator designs, we are targeting best in class latency with order of magnitude improvements for years to come.

Low Latency has become the key enabler for their industry and other real-time application and the current industry’ state-of-the art is just not up to the task. Client has been developing its Neural Net Engines accelerators, optimizing it for Latency and achieving the best LPPA (Latency, Performance, Power, Area) in the field. We are now building the corresponding SoC, to deliver unrivaled products to mission-critical and real-time applications.

This is a fast-paced, intellectually challenging position, and you will work with a talented team driven by innovation and excellency. You’ll have relentlessly high standards for yourself and everyone you work with, and you’ll be constantly looking for ways to improve our products' performance, quality and cost.

We’re changing the meaning of low latency and we want individuals ready to rise up to the challenge and take the industry by storm.

Job Responsibilities
Architect and build an SoC-level and unit-level UVM verification environment.
Collaborate with Architecture and Design teams to verify the SoC features according to the chip use scenario.
Construct the chip level test plans, develop either directed or constrained random test vectors for closing the target coverage.
Participate evaluating and selecting third-party VIPs and integrate them into the test bench.
Debug test failures by collaborating with stakeholders to identify the root cause of the issues.
Develop and maintain the daily and weekly regressions.

Required Skills
A minimum of 10+years (Principal) / 7+ years (Senior Staff) / 5+ years (Staff) of design verification experiencewith 1+ years of leader role (for Lead position).
Must possess prior experience in developing a complete chip-level UVM test bench from scratch (for principal / Lead role).
Expert in coverage driven System verilog UVM with DPI-C,including UVM runtime phases (for Lead/Principal role).
Proficient in programming in C/C++, python and/or scripting language.
Prior experience in ASIC design verification.
In-depth knowledge in bus fabrics; NoC, AMBA etc in multi-CPU environment.

Nice to have
Prior experience in verifying instruction driven designs like CPUs and GPGPUs.
Understanding of chip security, cold/warm boot sequences.
Experiences using SERDES based high speed interfaces, i.e. MIPI, PCIe and USB.
FPGA prototyping experience.
Knowledge in ISO-26262 ASIL compliances.

Education
BSEE/BSCE required
Master in Science preferred.

Featured benefits

• Medical insurance
• Vision insurance
• Dental insurance
• 401(k)