ASIC Design Verification Engineer

Broadcom; San Jose (CA); On-site; USD 141,000 - 225,000; Full time

Job summary

Join a forward-thinking company dedicated to developing cutting-edge silicon products for Ethernet systems in the Cloud. This role offers the chance to work with a stable team focused on creating devices that enhance AI/ML workflows. As a Constrained Random Design Verification engineer, you will utilize your expertise in SystemVerilog and UVM to verify innovative designs and contribute to a collaborative environment. The position not only promises a competitive salary but also a comprehensive benefits package, making it an excellent opportunity for seasoned professionals looking to make a significant impact in the tech industry.

Benefits

Medical, dental, and vision plans

401(k) with company matching

Employee Stock Purchase Program

Employee Assistance Program

Paid holidays

Sick leave

Vacation

Qualifications

• 12+ years of related experience in Design Verification.
• Expertise in constrained random verification methodologies.

Responsibilities

• Verify rapidly evolving designs using SystemVerilog and UVM.
• Participate in all aspects of Design Verification and technical leadership.

Skills

Self-motivated with a strong commitment to quality

Team player with excellent collaboration skills

Constrained random verification methodologies

SystemVerilog

UVM

Familiar with OOP

Education

Bachelor's Degree

Tools

SystemVerilog

UVM

VCS

Incisive

Python

Perl

Job description

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Job Description

Join a stable team developing silicon products for Ethernet systems in the Cloud, creating devices that accelerate AI/ML workflows! This team develops high throughput Ethernet solutions that deliver exceptional performance with power efficiency.

We seek highly skilled Constrained Random Design Verification engineers to verify rapidly evolving designs using industry-proven methodologies with SystemVerilog and UVM. Become part of an expert team of engineers involved in all aspects of Design Verification and potential technical leadership.

Required Skills

• Self-motivated with a strong commitment to quality
• Team player with excellent collaboration skills
• Experience with constrained random verification methodologies and coverage closure
• Preferably skilled in SystemVerilog and UVM, familiar with OOP

Tools and Languages

SystemVerilog (including class, SVA, etc.), UVM, VCS, Incisive, scripting skills (Python, Perl, ...)

Experience & Education

Bachelor's Degree and at least 12+ years of related experience.

Additional Information

Compensation & Benefits

The annual base salary ranges from $141,000 to $225,000. The position is eligible for a discretionary annual bonus and equity awards, following company policies. Broadcom offers a comprehensive benefits package including medical, dental, vision plans, 401(k) with company matching, Employee Stock Purchase Program, Employee Assistance Program, paid holidays, sick leave, and vacation. The company complies with all applicable laws regarding leaves of absence.

Equal Opportunity Employer

Broadcom is committed to diversity and equal opportunity. We consider all qualified applicants regardless of race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability, medical condition, pregnancy, veteran status, or other protected characteristics. Applicants with arrest and conviction records will be considered in accordance with local laws.

Additional Notes

If located outside the USA, please provide a home address for future correspondence.