ASIC Design Verification Engineer

Broadcom; Irvine (CA); On-site; USD 129,400 - 207,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

401(K) participation including company matching

Employee Stock Purchase Program (ESPP)

Paid sick leave and vacation time

Job summary

Broadcom in Irvine, California is seeking a Constrained Random Design Verification Engineer to join a stable team developing silicon products for Ethernet systems. The role involves verifying new designs and collaborating with global teams to develop cutting-edge products.

The ideal candidate will have a Bachelor's degree with 12+ years of experience, or a Master's with 10+, or a PhD with 3+. Strong teamwork, System Verilog and UVM skills are essential. The position includes a competitive salary and comprehensive benefits package.

Qualifications

• Experience in driving completion via coverage closure.
• Preferable skills in Object-oriented programming.
• Familiarity with scripting languages is a plus.

Responsibilities

• Verify new designs in a dynamic market.
• Collaborate with worldwide design and architecture teams.
• Engage in all aspects of Design Verification.

Skills

Self motivated

Strong teamwork

Constrained random verification methodologies

Coverage closure

Education

Bachelor's degree and 12+ years experience

Master's degree and 10+ years experience

PhD and 3+ years experience

Tools

System Verilog

UVM

VCS

Incisive

Python

Perl

Job description

Would you like to become part of a stable team developing silicon products for Ethernet systems in the Cloud? Come join this team creating devices that accelerate AI/ML workflows! This team develops high throughput Ethernet solutions that deliver unprecedented performance at critically important power efficiency.

We are looking for highly skilled and efficient Constrained Random Design Verification engineers that want to verify new designs that can evolve rapidly at every generation in a very dynamic market using industry proven methodologies using System Verilog and UVM. You can become a member of an extremely skilled and efficient group of engineers.

This is a rare opportunity to be part of a team that leads products for a new line of devices. The candidate will work with our worldwide design and architecture teams to develop leading edge products. All aspects of Design Verification will be involved, along with opportunities for technical leadership.

Skills: Self motivated personality with a strong presence to do things right. Need to have a strong sense of teamwork and ability to work well with other. Constrained random verification methodologies with experience driving completion via coverage closure.

Preferable to have skills with SV and UVM, well versed in OOP.

Tools/Languages: System Verilog (TB structures - Class, SVA, etc.), UVM, VCS, Incisive, Scripting skills a + (Python, Perl, …).

Experience: Bachelors and 12+ years of related experience or Masters degree and 10+ years of related experience or PhD and 3+ years of related experience.

Compensation And Benefits: The annual base salary range for this position is $129,400.00 - $207,000.00. This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

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