SOC Design Verification Engineer – Data Center Solutions

Qualcomm; San Diego (CA); On-site; USD 115,600 - 173,400; Full time

Benefits offered by this job

Discretionary bonus program

Annual RSU grants

Job summary

Qualcomm is seeking experienced Design Verification Engineers to join their Data Center SoC Verification team in San Diego, California. This role involves working on next-generation Data Center SoCs that power AI and cloud infrastructure.

The ideal candidate will be responsible for developing verification strategies, creating test scenarios, and ensuring first-silicon success for complex SoC designs. The position offers a competitive salary range of $115,600.00 – $173,400.00 plus bonuses and stock options.

Qualifications

• Minimum 2+ years of design verification experience; senior positions offered to candidates with proven expertise.
• Experience developing verification environments from architecture/specification through signoff.
• Strong understanding of computer architecture and digital design fundamentals.

Responsibilities

• Develop and execute comprehensive verification plans for SoC, subsystem, and IP‑level features.
• Design and implement scalable System Verilog/UVM‑based verification environments.
• Drive coverage closure using functional and code coverage metrics.

Skills

System Verilog

UVM

C

assertion-based verification

debugging

communication skills

Education

Bachelor's or master's degree in electrical engineering, computer engineering, computer science, or related field

Tools

Python

Portable Stimulus (PSS)

Emulation platforms (Veloce, Palladium, ZeBu)

Job description

Overview

We are seeking highly motivated and experienced Design Verification Engineers to join our Data Center SoC Verification team. In this role, you will be responsible for verifying next‑generation Data Center SoCs that power AI, high‑performance computing, and cloud infrastructure products. You will work closely with architects, design engineers, software teams, and verification specialists to develop scalable verification solutions, drive verification closure, and ensure first‑silicon success for complex SoC designs.

Key Responsibilities

• Develop and execute comprehensive verification plans for SoC, subsystem, and IP‑level features.
• Design and implement scalable System Verilog/UVM‑based and processor‑based verification environments.
• Create directed and constrained‑random test scenarios to validate functionality and architectural use cases.
• Develop assertions, functional coverage models, and checkers.
• Debug RTL, testbench, and integration issues and work closely with design teams to resolve defects.
• Drive coverage closure using functional and code coverage metrics.
• Participate in architecture and design reviews to ensure verification requirements are incorporated early in the development cycle.
• Verify complex Data Center SoC features including:
  • Multi‑core CPU systems
  • Cache coherency and interconnect fabrics
  • DDR/HBM memory subsystems
  • PCIe, CXL, Ethernet, and high‑speed interfaces
  • Security, RAS, and power‑management features
• Support emulation and acceleration‑based verification when required.
• Contribute to methodology improvements, automation, reusable verification components, and AI‑assisted verification flows.

Qualifications

• Bachelor's or master's degree in electrical engineering, computer engineering, computer science, or related field.
• Minimum 2+ years of design verification experience; senior positions offered to candidates with proven expertise.
• Strong knowledge of System Verilog, UVM, C, assertion‑based verification, coverage‑driven verification, and system‑level use‑case verification.
• Experience developing verification environments from architecture/specification through signoff.
• Strong understanding of computer architecture and digital design fundamentals.
• Experience debugging complex SoC‑level issues.
• Excellent communication and collaboration skills.

Preferred Qualifications

• Experience with one or more of the following:
  • CPU verification
  • Cache coherency protocols (ACE, CHI, CXL)
  • DDR or HBM memory systems
  • PCIe, Ethernet, or networking protocols
  • AI/ML accelerator verification
  • Security and RAS feature verification
  • System performance verification
  • System power verification
  • ATE and post‑silicon bring‑up testing
• Experience with:
• Portable Stimulus (PSS)
• Formal Verification
• Emulation platforms (Veloce, Palladium, ZeBu)
• Power‑aware verification
• Proficiency in Python or scripting languages for automation.
• Experience with AI‑assisted verification of workflows and test generation.
• Experience in full‑chip or subsystem verification environments.

Preferred Candidate Profile

The ideal candidate is a hands‑on verification engineer who is passionate about solving complex technical challenges and delivering high‑quality silicon. They should possess strong debugging skills, a solid understanding of SoC architecture, and the ability to thrive in a fast‑paced, collaborative environment.

Pay & Benefits

Pay range: $115,600.00 – $173,400.00. In addition to base salary, this role offers a competitive discretionary bonus program and an opportunity for annual RSU grants.

Equal Employment Opportunity

Qualcomm is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Accessibility

Qualcomm is committed to providing an accessible hiring process for individuals with disabilities. For accommodation requests, please contact disability‑[e-mail].