ASIC Design Engineer, SDC/STA — Hybrid

Cisco Systems, Inc.; San Jose (CA); Hybrid; USD 160,000 - 210,000; Full time

Benefits offered by this job

Life insurance

Vision insurance

Parental leave

Paid holidays

Sick time

401(k)

Job summary

Cisco Systems, Inc. in San Jose, CA is seeking an ASIC Design Hardware Engineer - SDC/STA (Hybrid) to develop timing constraints at block and full-chip levels and guide front-end and back-end teams toward timely design closure.

You will work with the Cisco Silicon One team on timing, SDC/STA tools like Primetime and TimeVision, Verilog/SystemVerilog, and scripting (TCL). The role offers a hybrid work model, competitive salary, and comprehensive benefits; the application window closes 09/24/2026.

Qualifications

• Bachelor's Degree in Electrical or Computer Engineering with 4+ years of ASIC or related experience or Master's Degree with 2+ years of ASIC or related experience.
• Experience with synthesis tools (eg. Synopsys DC/DCG/FC), STA tools such as Primetime and must have knowledge of HDL such as Verilog/SystemVerilog programming, and scripting languages such as Shell, Perl, and TCL.
• Experience with digital design concepts (clocking, timing exceptions and async boundaries).
• Experience with block/full chip SDC development in functional and test modes.
• Experience with microarchitecture and RTL implementation.

Responsibilities

• Being a member of design team who develops block level and full-chip SDCs and works with physical design and DFT teams to close full-chip timing in multiple timing modes.
• Work with design and architecture teams in understanding clocking structure, develop timing constraints and validate them through constraints verification tool before releasing them for physical design.
• Option to also do block level RTL design or block or top-level IP integration.
• Helping develop efficient methodology to promote block level SDCs to full-chip, and to push down full-chip SDCs to block level.
• Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
• Reviewing block level SDCs and clocking diagrams and collaborate with RTL design owners on SDC development.
• Contribute to full-chip clocking design including diagrams and related documentation.

Skills

Verilog/SystemVerilog

Scripting TCL

Primetime

TimeVision

SDC/STA tooling

Clocking concepts

RTL implementation

Synthesis tools (Synopsys)

Education

Bachelor's Degree in Electrical or Computer Engineering

Master's Degree in Electrical or Computer Engineering

Tools

Primetime

TimeVision

Synopsys DC/DCG/FC

Job description

Cisco Systems, Inc. in San Jose, CA is seeking an ASIC Design Hardware Engineer - SDC/STA (Hybrid) to develop timing constraints at block and full-chip levels and guide front-end and back-end teams toward timely design closure.

You will work with the Cisco Silicon One team on timing, SDC/STA tools like Primetime and TimeVision, Verilog/SystemVerilog, and scripting (TCL). The role offers a hybrid work model, competitive salary, and comprehensive benefits; the application window closes 09/24/2026.