ASIC Design and Integration Engineer – Silicon Security

Anysilicon; Cupertino, Northern (CA, KY); Hybrid; USD 120,000 - 160,000; Full time

Job summary

Apple's Silicon Security team seeks an ASIC Design Engineer to develop secure subsystems for the Apple SoC. This role involves designing advanced hardware defenses against side channel attacks and safeguarding sensitive customer data across Apple products.

Responsibilities include integrating security IPs into secure subsystems, ensuring compliance with timing, performance, and security standards, and driving front-end quality flows from RTL to netlist.

Qualifications

• BS in Electrical Engineering or Computer Engineering, or a relevant field.
• 0 years of experience required.

Responsibilities

• Architect and design security features with Platform Architecture and Verification teams.
• Integrate security IPs into secure subsystems meeting timing, performance, and security standards.
• Resolve integration issues across IP blocks and coordinate with IP owners on interfaces and functionality.
• Drive front-end quality flows from RTL to netlist, including Lint, CDC/RDC analysis, UPF development, timing and synthesis.
• Utilize AI-assisted tools to improve design quality and productivity.

Skills

RTL design

CDC/RDC analysis

UPF

Synthesis & timing

Cryptography

Hardware security

Clock/Reset architecture

AMBA (AXI/AHB/APB)

Education

Bachelor's degree in Electrical/Computer Engineering

Job description

ASIC Design and Integration Engineer – Silicon Security

Apple's Silicon Security team is seeking an ASIC Design Engineer to develop secure subsystems that safeguard the Apple SoC. This role involves designing advanced hardware defenses against side channel attacks, ensuring the protection of sensitive customer data across Apple products.

Responsibilities:

• Architect and design cutting-edge security features in collaboration with Platform Architecture and Design Verification teams.
• Integrate security IPs into secure subsystems, ensuring compliance with timing, performance, and security standards.
• Resolve integration issues across multiple IP blocks and coordinate with IP owners regarding interface and functionality.
• Drive front-end quality flows from RTL to netlist, including hands-on work with Lint, CDC/RDC analysis, UPF development, timing, and synthesis.
• Utilize AI-assisted tools to improve design quality and productivity.

Qualifications:

• BS in Electrical Engineering, Computer Engineering, or a relevant field.
• 0 years of experience.

Skills:

• RTL design experience using Verilog or SystemVerilog.
• Experience with CDC and RDC analysis and verification.
• Familiarity with low-power design techniques and UPF.
• Solid understanding of digital design fundamentals including synthesis, timing closure, and design for testability.
• Background in cryptography and cryptographic algorithm implementation.
• Knowledge of hardware security concepts including key management and physical attack countermeasures.
• Experience with clock and reset architecture at the subsystem level.
• Strong knowledge of AMBA bus protocols (AXI, AHB, APB).

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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