ASIC Architect

Delos Data Inc; EE. UU.; A distancia; USD 170.000 - 210.000; Jornada completa

Descripción de la vacante

Delos Data Inc. is seeking a senior ASIC architect to define architecture for high‑performance ASICs, spanning IP blocks to SoC integration for AI acceleration and datacenter workloads. You will build performance models and evaluate options to balance power, performance, and area.

Collaborating with RTL, verification, physical design, firmware, and software teams, you will lead technical trade‑offs and define power-management approaches while mentoring engineers across the organization.

Formación

• Bachelor’s degree in electrical engineering, computer engineering, or computer science.
• 7+ years of experience in ASIC architecture, microarchitecture, or high-level design.
• Proficiency in Verilog or SystemVerilog and C/C++ or SystemC modeling.

Responsabilidades

• Create architectural and microarchitecture specifications for complex ASICs, including interconnect fabrics and high-speed I/O.
• Build performance models with tools such as SystemC/TLM, C++, or Python to test assumptions against workloads.
• Evaluate architecture options and optimize block-level and chip-level designs for power, performance, and area.
• Coordinate with RTL, verification, physical design, firmware, and software teams through implementation and validation.
• Lead technical trade-off reviews and define power-management approaches, including dynamic voltage and frequency scaling, power domains, and clock gating.
• Provide technical leadership and mentorship to other engineers.

Conocimientos

ASIC architecture

SystemVerilog

C/C++/SystemC modeling

Power-performance-area optimization

Technical leadership

Educación

Bachelor’s degree in EE/CE/CS

Herramientas

SystemC

SystemVerilog

EDA tools

Descripción del empleo

Role overview

Define the architecture of high-performance ASICs, converting system needs into detailed architectural and microarchitectural specifications. The role spans IP blocks, subsystems, and SoC integration for AI acceleration, networking, and datacenter workloads, balancing power, performance, and area while guiding implementation across engineering teams.

Responsibilities

• Create architectural and microarchitecture specifications for complex ASICs, including interconnect fabrics and high-speed I/O.
• Build performance models with tools such as SystemC/TLM, C++, or Python to test assumptions against workloads.
• Evaluate architecture options and optimize block-level and chip-level designs for power, performance, and area.
• Coordinate with RTL, verification, physical design, firmware, and software teams through implementation and validation.
• Lead technical trade-off reviews and define power-management approaches, including dynamic voltage and frequency scaling, power domains, and clock gating.
• Provide technical leadership and mentorship to other engineers.

Requirements

• Bachelor’s degree in electrical engineering, computer engineering, or computer science.
• At least seven years of experience in ASIC architecture, microarchitecture, or high-level design.
• Proficiency in Verilog or SystemVerilog and C/C++ or SystemC modeling.
• Strong understanding of processor and accelerator cores, caches, interconnects, and memory hierarchies.
• Experience with protocols such as Ethernet, PCIe, or UAL, and familiarity with EDA tools and performance analysis.

Nice to have

• A master’s degree or doctorate, and experience in AI accelerators or high-performance networking silicon.
• A record of taking high-performance silicon from concept through tape-out, or experience with pre-silicon emulation.
• Scripting skills in Python, Tcl, or Perl, along with strong communication, independent problem-solving, and mentoring skills.