Architect

delos-data; Palo Alto (CA); On-site; USD 160,000 - 280,000; Full time

Benefits offered by this job

Equity

Benefits

401k

Job summary

delos-data is seeking an ASIC Architect to define and guide the development of next-generation high-performance ASICs for AI accelerators and datacenter workloads. You’ll translate requirements into architectural specs, balancing power, performance, and area, and partner across RTL, verification, and software teams.

You’ll drive ADS/MAS development, build performance models, and lead design reviews while mentoring junior engineers. This is a hybrid role in the Silicon Valley area.

Qualifications

• Bachelor’s degree in Electrical/Computer Engineering or CS.
• 7+ years in ASIC architecture, micro-architecture, or high-level design.
• Strong proficiency in SystemVerilog/Verilog and C/C++ or SystemC modeling.
• Deep knowledge of CPU/GPU cores, caches, fabric, memory hierarchies.
• Experience with Ethernet, PCIe, UCIe protocols and EDA tools.

Responsibilities

• Lead creation of Architectural Design Specifications and MAS for complex ASICs.
• Develop high-level performance models to analyze workloads and validate assumptions.
• Optimize architecture to meet power, performance, and area goals.
• Collaborate with RTL, verification, physical design, firmware, and software teams.
• Drive trade-off studies and lead design reviews.
• Define advanced power management strategies including DVFS and clock gating.
• Mentor junior engineers and provide technical leadership.

Skills

SystemVerilog/Verilog proficiency

C/C++/SystemC modeling

Architecture design

Leadership

Education

Bachelor’s degree in Electrical/Computer Engineering or CS

Master’s degree or PhD (desirable)

Tools

SystemVerilog/Verilog

C/C++

SystemC

EDA tools (Synopsys Genus, Design Compiler)

Ethernet, PCIe, UCIe protocols

Job description

ASIC ARCHITECT

We are seeking a highly skilled and visionary ASIC Architect to define, architect, and guide the development of next-generation, high-performance ASICs. As a key technical leader, you will translate high-level system requirements into detailed architectural specifications, balancing power, performance, and area (PPA) trade-offs.

We are a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors. The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver. Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.

What we need:

We are seeking a highly skilled and visionary ASIC Architect to define, architect, and guide the development of next-generation, high-performance ASICs. As a key technical leader, you will translate high-level system requirements into detailed architectural specifications, balancing power, performance, and area (PPA) trade-offs. You will work across teams to define the architecture for IP blocks, sub-systems, and full SoC integration for advanced AI accelerators, networking, and datacenter computing workloads.

Key Responsibilities:

• Lead the creation of Architectural Design Specifications (ADS) and Micro-architecture Specifications (MAS) for complex ASICs including high-speed interconnect fabric and IO protocols (Ethernet, PCIe, UCIe).
• Develop high-level performance models (using SystemC/TLM, C++, or Python) to analyze workload behaviors and validate architectural assumptions.
• Optimize chip-level and block-level architecture to meet stringent power, performance, and area goals.
• Partner with RTL design, verification, physical design, firmware, and software teams to ensure seamless implementation and validation.
• Drive architectural trade-off studies and lead design reviews.
• Define advanced power management strategies including DVFS, power domains, and clock gating.
• Mentor junior engineers and contribute to technical leadership across the organization.

Required Skills and Qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science
• 7+ years of experience in ASIC architecture, micro-architecture, or high-level design.
• Strong proficiency in SystemVerilog/Verilog and C/C++ or SystemC for modeling.
• Deep knowledge of computer architecture, including CPU/GPU cores, caches, fabric, and memory hierarchies.
• Experience with industry-standard protocols such as Ethernet, PCIe or UAL.
• Familiarity with EDA tools such as Synopsys Design Compiler, Cadence Genus, or similar.
• Experience with performance modeling and analysis tools.

Desired Skills:

• Master’s degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
• Experience designing AI/ML accelerators or high-performance networking silicon.
• Proven record of shipping high-performance silicon from concept to tape-out.
• Familiarity with pre-silicon emulation platforms.
• Strong scripting skills (Python, Tcl, Perl) for automation.
• Excellent communication skills and ability to articulate complex architectural concepts.
• Proactive problem solver capable of working with minimal oversight.
• Strong leadership and mentorship capabilities

Compensation:

Target base salary for this role is $160,000 - $280,000 per year + meaningful equity + benefits + 401k. Our salary ranges are determined by role, level, experience, and location.