Remote ASIC Verification Engineer: UVM + GLS Expert

CBL Solutions; United States; Remote; USD 120,000 - 170,000; Full time

Job summary

CBL Solutions is seeking an ASIC Verification Engineer focused on UVM and GLS to join a remote-friendly team. You will lead verification of complex ASIC/SoC blocks, designing verification components and sign-off criteria in a zero-defect mindset.

Your remit includes building UVM environments from scratch, executing GLS with timing analyses, and driving regression automation. Remote work is acceptable, with the engagement lasting 12+ months.

Qualifications

• Experience building complete UVM verification environments from scratch.
• Extensive gate-level simulation (GLS) with SDF annotation and timing validation.
• Expert-level proficiency in SystemVerilog and UVM for ASIC/SoC verification.
• Preferred knowledge of Ethernet, PCIe, or UCIe protocols.

Responsibilities

• Own verification of complex ASIC/SoC design blocks from planning through sign-off.
• Develop UVM-based verification environments from scratch, including testbench infrastructure, agents, drivers, monitors, scoreboards, sequences, and coverage models.
• Execute and debug GLS, including timing-related failures, SDF-annotated simulations, reset issues, X-propagation, and initialization/debug challenges.
• Perform deep waveform analysis, root-cause debugging, regression triage, and verification sign-off activities.

Skills

UVM verification

GLS experience

SystemVerilog

Testbench architecture

Job description

CBL Solutions is seeking an ASIC Verification Engineer focused on UVM and GLS to join a remote-friendly team. You will lead verification of complex ASIC/SoC blocks, designing verification components and sign-off criteria in a zero-defect mindset.

Your remit includes building UVM environments from scratch, executing GLS with timing analyses, and driving regression automation. Remote work is acceptable, with the engagement lasting 12+ months.