Analog & Mixed-Signal Layout Designer

Socket.dev; Cupertino (CA); On-site; USD 149,000 - 218,000; Full time

Benefits offered by this job

Stock options

RSU awards

Discounted products

Education reimbursement

Relocation assistance

Job summary

Apple is seeking a skilled layout engineer to design complex mixed-signal and analog circuits in deep sub-micron CMOS technologies. You will review floorplans with circuit designers, run verification tools, and collaborate on planning and scheduling work.

The role requires mastering LVS, DRC, and ERC checks to achieve the best possible layout. The position is based in Cupertino with a 40-hour work week and a base pay range reflective of senior engineering roles.

Qualifications

• Master’s degree or foreign equivalent in Electrical Engineering or related field.
• Experience with ICManage for project configuration and LEF navigation.
• Proficient with Voltus for EMIR checks and debugging.
• Ability to create leaf cells and floorplans for analog/mixed-signal designs.
• Experience analyzing RC extraction to debug layout mismatches.
• Ability to identify critical signals through schematic ID.
• Provide recommendations on design rules and technology impact.
• Proficient with PDV to debug DRC/LVS issues and fix errors.
• Proficient with Virtuoso for layout editing and data management.

Responsibilities

• Design complex circuit layout for mixed-signal and analog circuits in deep sub-micron CMOS.
• Review floorplans and circuits with designers to optimize performance.
• Run verification tools for analog/mixed-signal blocks.
• Collaborate with circuit design teams to plan work.Interpret LVS, DRC, and ERC checks to achieve optimal layout.

Skills

Floorplanning

RC extraction

Schematic ID

Technology impact recommendations

Analog mixed-signal layouts

High-speed analog design

Education

Master’s degree in Electrical Engineering

Tools

ICManage

Voltus

PDV

Virtuoso

Job description

Apple is seeking a skilled layout engineer to design complex mixed-signal and analog circuits in deep sub-micron CMOS technologies. You will review floorplans with circuit designers, run verification tools, and collaborate on planning and scheduling work.

The role requires mastering LVS, DRC, and ERC checks to achieve the best possible layout. The position is based in Cupertino with a 40-hour work week and a base pay range reflective of senior engineering roles.