Layout/Mask Designer

Socket.dev; Cupertino (CA); On-site; USD 149,000 - 218,000; Full time

Benefits offered by this job

Stock options

RSU awards

Discounted products

Education reimbursement

Relocation assistance

Job summary

Apple is seeking a skilled layout engineer to design complex mixed-signal and analog circuits in deep sub-micron CMOS technologies. You will review floorplans with circuit designers, run verification tools, and collaborate on planning and scheduling work.

The role requires mastering LVS, DRC, and ERC checks to achieve the best possible layout. The position is based in Cupertino with a 40-hour work week and a base pay range reflective of senior engineering roles.

Qualifications

• Master’s degree or foreign equivalent in Electrical Engineering or related field.
• Experience with ICManage for project configuration and LEF navigation.
• Proficient with Voltus for EMIR checks and debugging.
• Ability to create leaf cells and floorplans for analog/mixed-signal designs.
• Experience analyzing RC extraction to debug layout mismatches.
• Ability to identify critical signals through schematic ID.
• Provide recommendations on design rules and technology impact.
• Proficient with PDV to debug DRC/LVS issues and fix errors.
• Proficient with Virtuoso for layout editing and data management.

Responsibilities

• Design complex circuit layout for mixed-signal and analog circuits in deep sub-micron CMOS.
• Review floorplans and circuits with designers to optimize performance.
• Run verification tools for analog/mixed-signal blocks.
• Collaborate with circuit design teams to plan work.Interpret LVS, DRC, and ERC checks to achieve optimal layout.

Skills

Floorplanning

RC extraction

Schematic ID

Technology impact recommendations

Analog mixed-signal layouts

High-speed analog design

Education

Master’s degree in Electrical Engineering

Tools

ICManage

Voltus

PDV

Virtuoso

Job description

Description

Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA.

• Design complex circuit layout for mixed signal, and analog circuits in deep sub-micron CMOS technologies.
• Review and analyze floorplans and complex circuits with circuit designers.
• Run complete set of design verification tools available on analog/mixed-signals blocks.
• Work with circuit design and other teams to plan/schedule work.
• Interpret checks including LVS, DRC and ERC to find the fastest way to complete layout and work on getting the best layout possible for the circuit.
• Work on achieving set of specifications for a particular circuit.
• 40 hours/week.

The base pay range for this role is between $148,987 - $218,000/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan.

• Comprehensive medical and dental coverage
• retirement benefits
• a range of discounted products and free services
• reimbursement for certain educational expenses — including tuition.
• Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation.

Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

• Master’s degree or foreign equivalent in Electrical Engineering or related field and 1 year of experience in the job offered or related occupation.
• Experience and/or education must include: Using ICManage tool to navigate and create project related technology config, workspace, LEF (Library Exchange Format).
• Using Voltus to navigate, debug and fix EMIR violations.
• Creating leaf cell and block level Floorplan in various designs (analog mixed signal and high-speed analog) and making connections (transistors, clock signals and data-path).
• Analyzing RC (resistance & capacitance) extraction to debug and fix layout mismatches.
• Performing schematic ID by identifying critical signals (high speed, static/dynamic, high current).
• Providing circuit designers with recommendations on technology impact (know what design rule checks (DRC) are possible or not.
• Using PDV tool to debug and fix complex DRC and LVS violations: Latch-up, ESD, transistor hookup errors & short circuits.
• Using Virtuoso tool to efficiently create various groups, width/Space patterns (WSP), toolbar, layout editor, layer manipulation, check in & check out data, XL compliant.