CAD and Integration Engineer, Silicon

Meta; Sunnyvale (CA); On-site; USD 212,000 - 294,000; Full time

Job summary

Meta is seeking a CAD and Integration Engineer to join the custom silicon team in Sunnyvale. You will translate circuit intent into physical constraints, drive RTL-to-GDS flows, and signoff while enabling 3D stacking across nodes.

You will build automation tools, improve CAD flows, and leverage AI-assisted design to accelerate engineering velocity across multidisciplinary teams.

Qualifications

• Bachelor's degree or higher in CS/EE or equivalent practical experience.
• 12+ years of industry experience in analog CAD/automation and tapeouts.
• Expertise in full RTL-to-GDS flow, digital synthesis, PNR, and physical signoff.
• Proficiency in analog mixed signal design environment and simulation tools.
• Knowledge of PDK and Spice model qualification.
• Strong programming skills to automate design tasks (SKILL, Python, Perl).
• Hands-on experience with AI coding assistants.
• Experience communicating decisions to cross-functional partners.

Responsibilities

• Integrate AI/LLM tools into design workflows to boost automation and productivity
• Lead analog mixed-signal physical integration and enforce constraints with design/layout teams
• Manage end-to-end digital implementation flows (RTL-to-GDS): synthesis, PNR, DFT, signoff
• Drive physical signoff (timing, power, verification) for foundry-ready deliverables
• Develop 3D stacking flows for heterogeneous integration and cross-die timing/power analysis
• Automate implementation, tapeout, and regression using Python, SKILL and Tcl

Skills

Analog design

Automation scripting

AI coding assistants

Cross-functional communication

Education

Bachelor's degree in CS/EE or related field

BS/MS/PhD in EE/CE or related field with 12+ years of experience

Tools

SKILL

Python

Perl

Job description

Summary:

We are looking for a CAD and Integration Engineer to join our custom silicon team. Working in close partnership with circuit designers, digital designers and layout engineers, you will translate circuit intent into physical constraints, drive synthesis, place-and-route, and signoff, and bridge the gap between schematic and silicon. You will also play a key role in enabling 3D stacking flows between heterogeneous process nodes. Beyond implementation, we expect a builder's mindset: developing automation tools, improving CAD flows, and actively leveraging AI-assisted design to increase team-wide engineering velocity.

Required Skills:

CAD and Integration Engineer, Silicon Responsibilities:

1. Integrate AI/LLM tools into workflows to drive design automation and engineering productivity
2. Lead analog mixed signal physical integration and enforce design constraints in collaboration with design and layout teams
3. Manage end-to-end digital implementation flows (RTL-to-GDS), including synthesis, PNR, DFT insertion, and signoff
4. Drive physical signoff (timing, power, verification) to ensure foundry-ready deliverables
5. Develop 3D stacking flows for heterogeneous integration and die-to-die interface planning, cross-die timing and power analysis
6. Automate implementation, tapeout, and regression using Python, SKILL, and Tcl

Minimum Qualifications:

Minimum Qualifications:

1. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
2. BS/MS/PhD in EE, CE, or a related field with 12+ years of industry experience
3. Proven industry experience in analog CAD/automation support areas involving various technology nodes and tapeouts
4. Expertise in full RTL-to-GDS flow, digital synthesis, PNR, and physical signoff
5. Proficiency in analog mixed signal design environment and simulation tools
6. Knowledge of PDK and Spice model qualification
7. Strong programming skills in languages such as SKILL, Python, Perl etc. to provide automation needs
8. Hands-on experience with AI coding assistants
9. Experience communicating technical decisions and project status to cross-functional partners, including circuit designers, layout engineers, and foundry contacts

Preferred Qualifications:

Preferred Qualifications:

1. Familiarity with advanced packaging technologies and their implications for chip-level CAD methodology and integration flows
2. Experience with hierarchical chip integration and assembly flows for large, multi-block SoCs targeting consumer electronics or wearable device applications
3. Experience with low-power design methodologies including multi-voltage domain integration, UPF-based power intent, and power analysis sign-off for mobile or wearable silicon
4. Experience engaging directly with foundry partners on process design kit development, design rule updates, and technology qualification for leading-edge nodes

Public Compensation:

$212,000/year to $294,000/year + bonus + equity + benefits

Industry:

Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affline Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].