Analog Layout Engineer

ALKU; Tucson (AZ); On-site; USD 80,000 - 120,000; Part time

Benefits offered by this job

Medical insurance

Vision insurance

401(k)

Job summary

A semiconductor design firm seeks an experienced Analog Layout Engineer for a contract position in Tucson, AZ. This mid-senior level role demands proficiency in full-custom analog layout design and experience with LBC9 and HPA9 process nodes. Responsibilities include performing high-quality layouts using Cadence Virtuoso and Calibre tools, while ensuring best practices for design efficiency. Benefits include medical and vision insurance and a 401(k).

Qualifications

• 5–10 years of hands-on experience in analog layout within semiconductor design.
• Proven expertise in advanced process nodes (LBC9 and HPA9).
• Strong familiarity with industry-standard verification tools.

Responsibilities

• Perform full-custom analog layout design for analog/mixed-signal products.
• Execute layouts using Cadence Virtuoso and Calibre, ensure compliance with best practices.
• Utilize proprietary design methodologies for high-precision analog IC layout.

Skills

Analog layout experience

Proficiency in Cadence Virtuoso

Expertise with LBC9 and HPA9 process nodes

Tools

Cadence Virtuoso suite

Calibre

Job description

We are seeking an experienced Analog Layout Engineer for a contract role in Tucson, AZ, to support high-precision analog IC layout using specific flows and process nodes.

Key Responsibilities

• Perform full-custom analog layout design for analog/mixed-signal products.
• Utilize proprietary design flows and methodologies on LBC9 (130-nm BCD/analog process) and HPA9 (high-performance analog node) technologies.
• Execute high-quality layouts using industry-standard tools (primarily Cadence Virtuoso suite for layout/schematic integration, Calibre for DRC/LVS/PEX verification, and related toolchain).
• Ensure best practices for matching, symmetry, parasitics, EM/IR, ESD, and density in analog designs.

Required Qualifications

• 5–10 years of hands‑on analog layout experience in semiconductor design.
• Proven expertise with LBC9 and HPA9 process nodes.
• Proficiency in analog layout tools, including Cadence Virtuoso suite and Calibre (or equivalent verification tools).

Seniority Level

Mid‑Senior level

Employment Type

Contract

Job Function

Design and Engineering

Industries

Semiconductor Manufacturing

Benefits

• Medical insurance
• Vision insurance
• 401(k)