Analog Layout Engineer

Inabia Software & Consulting Inc.; Texas; Híbrido; USD 120.000 - 180.000; Jornada completa

Descripción de la vacante

Arrow Electronics is seeking a Senior Analog Layout Engineer for Austin, TX. You will design the physical layout for high-speed mixed-signal blocks (SerDes, ADCs, DACs, PLLs) and drive floor planning and integration.

The role requires 7+ years in deep sub-micron CMOS/FinFET layouts, with experience in lower nodes (N3/N5) and strong skills in parasitic control, DRC/LVS/ERC, and EM/IR reliability.

Formación

• 7+ years of hands-on layout experience in deep sub-micron CMOS/FinFET.
• Experience with lower nodes (N3, N5) is critical.
• Familiarity with floor planning and block/top-level integration.

Responsabilidades

• Floor planning and chip-top level integration of high-speed blocks.
• Address layout-dependent effects, device matching, and shielding.
• Ensure reliability through DRC/LVS/ERC and EM/IR considerations.

Conocimientos

Analog layout

Floor planning

Parasitics control

DRC LVS ERC

High-speed design

CMOS FinFET

EDA tools

Descripción del empleo

Hello,

Job Title : Analog Layout Engineer

Client: Arrow Electronics

Experience Required:7+ years (Relevant)

Work Location: Austin ,TX (Remote)

Visa: All visa, except H1B transfer

C2C engagements are allowed.

TSMC 4NM (Must Have)

High-Speed Analog Layout Engineer designs the physical silicon layout for high-frequency or high-speed mixed-signal circuits (such as SerDes, ADCs, DACs, PLLs, and High speed blocks).

Floor Planning & Integration: Create block-level and chip-top-level floor plans, manage hierarchical block integration, and handle micro-bump or package-aware co-design

Parasitic & Noise Control: Address layout-dependent effects (LOD, WPE, LDE), device matching, common-centroid structures, guard rings, and isolation or shielding (coaxial, differential, ground shields). [1, 2, 3]

Reliability & Verification: Ensure complete closure on DRC (Design Rule Check), LVS (Layout Versus Schematic), ERC, antenna rules, EM/IR (Electromigration / Infrared drop) reliability, and ESD protection

Generally 5 to 12+ years of hands-on custom IC layout experience in deep sub-micron or advanced CMOS/FinFET nodes (such as TSMC N3, N5, N7)

Experience at Lower node (N3, N5) is critical for this position.