Analog Layout Engineer

Inabia Software & Consulting Inc.; Austin (TX); Remote; USD 120,000 - 180,000; Full time

Job summary

Inabia Software & Consulting Inc. in Austin, TX is seeking an experienced Analog Layout Engineer to design high‑speed analog blocks for cutting‑edge silicon (e.g., SerDes, PLLs, ADCs/DACs). You will own floor planning, parasitic and noise control, and reliability verification to ensure robust layouts.

The role requires 7+ years of hands‑on IC layout experience in deep sub‑micron CMOS (N3/N5) and practical exposure to DRC/LVS, with a focus on tight design rules and performance targets.

Qualifications

• 7+ years of hands-on analog/layout experience in deep sub-micron CMOS processes.
• Experience with DRC/LVS, ESD and layout verification.
• Strong understanding of parasitic and noise considerations in high-speed layouts.

Responsibilities

• Floor plan and integrate block-level to chip-top-level layouts.
• Address parasitic/LOD, WPE, LDE and device matching for high-speed blocks.
• Ensure DRC/LVS/ERC compliance and antenna rules.
• Maintain reliability against EMC/IR, ESD, and shielding concerns.
• Collaborate across teams to meet performance and area targets.

Skills

Analog IC layout

Floorplanning

Parasitic control

Reliability verification

CMOS/FinFET tech

Job description

• Job Title : Analog Layout Engineer
• Client: Arrow Electronics
• Experience Required:7+ years (Relevant)
• Work Location: Austin ,TX (Remote)
• Visa: All visa, except H1B transfer
• C2C engagements are allowed.

TSMC 4NM (Must Have)

High-Speed Analog Layout Engineer designs the physical silicon layout for high-frequency or high-speed mixed-signal circuits (such as SerDes, ADCs, DACs, PLLs, and High speed blocks).

• Floor Planning & Integration: Create block-level and chip-top-level floor plans, manage hierarchical block integration, and handle micro-bump or package-aware co-design
• Parasitic & Noise Control: Address layout-dependent effects (LOD, WPE, LDE), device matching, common-centroid structures, guard rings, and isolation or shielding (coaxial, differential, ground shields). [1, 2, 3]
• Reliability & Verification: Ensure complete closure on DRC (Design Rule Check), LVS (Layout Versus Schematic), ERC, antenna rules, EM/IR (Electromigration / Infrared drop) reliability, and ESD protection
• Generally 5 to 12+ years of hands-on custom IC layout experience in deep sub-micron or advanced CMOS/FinFET nodes (such as TSMC N3, N5, N7)
• Experience at Lower node (N3, N5) is critical for this position.