Analog Layout Engineer

Inabia-Software-; Austin (TX); A distancia; USD 120.000 - 180.000; Jornada completa

Descripción de la vacante

Arrow Electronics is seeking an experienced Analog Layout Engineer for TSMC 4NM designs in Austin, TX (Remote). You will design physical silicon layouts for high-speed analog blocks such as SerDes, ADCs, DACs, PLLs, and related blocks.

You will handle floor planning, parasitic/noise control, and reliability verification, with 7+ years in deep sub-micron nodes (N3/N5 preferred). Visa/remote options apply; C2C allowed.

Formación

• 7+ years of hands-on analog layout experience.
• Experience with deep sub-micron or advanced CMOS/FinFET nodes (N3/N5).
• Proficiency in floor planning, parasitic & noise control, DRC/LVS/ERC.
• Knowledge of layout-dependent effects and ESD protection is a plus.

Responsabilidades

• Floor planning & integration: create block-level and chip-top-level floor plans.
• Parasitic & noise control: address LOD, WPE, LDE and device matching.
• Reliability & verification: ensure DRC, LVS, ERC, antenna rules, EM/IR, ESD.
• Collaborate on layout for high-speed mixed-signal blocks (SerDes, ADC/DAC, PLLs).
• Work with sub-mystems across deep sub-micron nodes (N3/N5) as required.

Conocimientos

Analog Layout

Floor planning

Parasitic control

Reliability & verification

CMOS/FinFET knowledge

Descripción del empleo

• Job Title : Analog Layout Engineer
• Client: Arrow Electronics
• Experience Required:7+ years (Relevant)
• Work Location: Austin ,TX (Remote)
• Visa: All visa, except H1B transfer
• C2C engagements are allowed.

TSMC 4NM (Must Have)

High-Speed Analog Layout Engineer designs the physical silicon layout for high-frequency or high-speed mixed-signal circuits (such as SerDes, ADCs, DACs, PLLs, and High speed blocks).

• Floor Planning & Integration: Create block-level and chip-top-level floor plans, manage hierarchical block integration, and handle micro-bump or package-aware co-design
• Parasitic & Noise Control: Address layout-dependent effects (LOD, WPE, LDE), device matching, common-centroid structures, guard rings, and isolation or shielding (coaxial, differential, ground shields). [1, 2, 3]
• Reliability & Verification: Ensure complete closure on DRC (Design Rule Check), LVS (Layout Versus Schematic), ERC, antenna rules, EM/IR (Electromigration / Infrared drop) reliability, and ESD protection
• Generally 5 to 12+ years of hands-on custom IC layout experience in deep sub-micron or advanced CMOS/FinFET nodes (such as TSMC N3, N5, N7)
• Experience at Lower node (N3, N5) is critical for this position.