Analog Layout Engineer

Inabia Software & Consulting Inc.; Oregon; Hybrid; USD 120,000 - 180,000; Full time

Job summary

Arrow Electronics is seeking an Analog Layout Engineer in Austin, TX (Remote) to design the physical silicon layouts for high-speed, mixed-signal circuits such as SerDes, ADCs, DACs, and PLLs.

You will perform floor planning and integration, manage block-level designs, and address parasitic/noise control with shielding and device matching. A strong focus on DRC/LVS/ERC, antenna rules, EM/IR reliability, and ESD protection is required.

Qualifications

• 7+ years of hands-on analog IC layout experience in deep sub-micron or FinFET nodes.
• Experience with floor planning, integration, and package-aware co-design.
• Strong focus on parasitic and noise control and device matching.
• Experience with layout-dependent effects (LOD, WPE, LDE) and shielding.
• Familiarity with DRC/LVS/ERC, antenna rules, EM/IR reliability, and ESD protection.
• Experience with lower nodes (N3, N5) is critical.

Responsibilities

• Design physical silicon layout for high-frequency or high-speed mixed-signal circuits (SerDes, ADCs, DACs, PLLs).
• Floor Planning & Integration: create block-level and chip-top-level floor plans, manage hierarchical block integration, and handle micro-bump or package-aware co-design.
• Parasitic & Noise Control: address layout-dependent effects, device matching, common-centroid structures, guard rings, shielding (coaxial, differential, ground shields).
• Reliability & Verification: ensure complete closure on DRC, LVS, ERC, antenna rules, EM/IR reliability, and ESD protection.
• Generally 5 to 12+ years of hands-on custom IC layout experience in deep sub-micron or advanced CMOS/FinFET nodes (N3, N5, N7).
• Experience at Lower node (N3, N5) is critical for this position.

Skills

High-Speed Analog Layout

Floor Planning

Parasitic & Noise Control

Reliability & Verification

CMOS/FinFET Knowledge

Job description

Job Title :

Analog Layout Engineer

Client:

Arrow Electronics

Experience Required:

7+ years (Relevant)

Work Location:

Austin ,TX (Remote)

Visa

: All visa, except H1B transfer

C2C engagements are allowed.

TSMC 4NM (Must Have)

High-Speed Analog Layout Engineer designs the physical silicon layout for high-frequency or high-speed mixed-signal circuits (such as SerDes, ADCs, DACs, PLLs, and High speed blocks).

Floor Planning & Integration: Create block-level and chip-top-level floor plans, manage hierarchical block integration, and handle micro-bump or package-aware co-design

Parasitic & Noise Control: Address layout-dependent effects (LOD, WPE, LDE), device matching, common-centroid structures, guard rings, and isolation or shielding (coaxial, differential, ground shields). [1, 2, 3]

Reliability & Verification: Ensure complete closure on DRC (Design Rule Check), LVS (Layout Versus Schematic), ERC, antenna rules, EM/IR (Electromigration / Infrared drop) reliability, and ESD protection

Generally 5 to 12+ years of hands-on custom IC layout experience in deep sub-micron or advanced CMOS/FinFET nodes (such as TSMC N3, N5, N7)

Experience at Lower node (N3, N5) is critical for this position.