Digital Layout Design Engineer

Apple; Beaverton (OR); On-site; USD 120,000 - 160,000; Full time

Job summary

Apple in Beaverton, OR is seeking a Digital Layout Designer to join our silicon design team. You will design complex custom layouts for digital circuits in deep SubMicron CMOS, review floorplans with circuit designers, and use CAD tools to produce robust physical design.

Strong scripting skills and experience with CALIBRE DRC/ERC/LVS, Mentor Graphics or Cadence are a plus. A Bachelor's degree with 10 years of experience is expected, and the role is on-site at our Beaverton campus.

Qualifications

• Bachelor's degree in a relevant field and 10+ years of experience.
• Experience designing deep SubMicron CMOS layouts for ASICs.
• Strong layout floorplanning and standard cell planning proficiency.
• Ability to interpret RC delay, electromigration, self-heating, and cross capacitance issues.

Responsibilities

• Design complex custom layouts for digital circuits in deep SubMicron CMOS technologies.
• Review floorplans and complex circuits with circuit designers.
• Run layout verification toolchains (DRC/ERC/LVS) and iterate layouts.
• Collaborate with circuit designers to plan work and negotiate tradeoffs.
• Write and maintain layout scripts; use CAD tools for robust physical design.

Skills

Layout floorplanning

Standard cell planning

Hierarchical layout assembly

Communication skills

Team collaboration

CALIBRE DRC/ERC/LVS

Mentor Graphics or Cadence tools

Scripting: CSH/Perl/Skill

Education

Bachelor's degree in relevant field

Tools

CALIBRE

Mentor Graphics

Cadence

Job description

Summary

Do you have a passion for crafting entirely new solutions?As part of our Digital Design Engineering group, you’ll take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking ideas to the real world. Join us, and you’ll help design the tools that allow us to bring customers experiences they’ve never before envisioned.You will be part of an exciting silicon design group that is responsible for designing state-of-the-art ASICs. We have an extraordinary opportunity for Digital Layout Designers!In this highly visible role, you will be a member of Apple’s custom layout team, working on the latest technology nodes to create extraordinary custom digital macros, libraries, etc. This is a fast paced work environment with endless learning opportunities working in the design team with members of integration, CAD, circuit and technology engineering.

Description

Imagine yourself at the center of our SOC design effort, collaborating with all fields, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new ideas, as well as work with a team of hardworking engineers. As a member of the layout team of the microprocessor group, you will be responsible to deliver PDV clean layout, including the following:

• Designing complex custom layout for digital circuits in deep SubMicron CMOS technologies.
• Reviewing and analyzing floorplans and complex circuits with circuit designers.
• Running a complete set of layout design verification tools available on megacells completed.
• Working with the circuit design team to plan, schedule work and negotiate layout tradeoffs as needed.
• Interpretation of LVS, DRC and ERC report to find the fastest way to complete layouts.
• Exceed engineering specifications and expectations.
• Use advanced CAD tools, mask design knowledge to layout corrections and robust physical design representation of circuits.

Minimum Qualifications

Bachelors degree in relevant field of study plus 10 years of relevant experience

Preferred Qualifications

We are looking for applicants experience in custom layout design of deep SubMicron CMOS circuits.High level proficiency in layout floorplanning, standard cell planning and hierarchical layout assembly.Good understanding of issues with RC delay, electromigration, self heating and cross capacitance.Recognize failure prone layout structures, dedicatedly work with designers for the best approach to problems.Excellent communication skills and able to work with multi-functional teams.Great skills on interpretation of CALIBRE DRC, ERC, LVS, etc. reports.Knowledge of MENTOR GRAPHICS or CADENCE layout toolsScripting skills in CSH, PERL or SKILL are considered a plus, but not required.Experience in layout automation is considered a plus, but not required.Experience in memory compiler development is considered a plus, but not required.Experience designing low noise, low power datapaths or Memory layout structures, etc.