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Teradyne's Semiconductor Test Division in Agoura Hills, CA is seeking an Analog Design Engineer to develop high-speed analog and mixed-signal ASICs for Automatic Test Equipment (ATE).
Candidates will design from spec to transistor-level, validate with Cadence tools, and collaborate across AI-enabled design teams to accelerate semiconductor innovation.
Strong background in CMOS, FinFET, and high-frequency IC design, plus scripting in Python or SKILL, is highly valued.
Teradyne's Semiconductor Test Division in Agoura Hills, CA is seeking an Analog Design Engineer to develop high-speed analog and mixed-signal ASICs for Automatic Test Equipment (ATE).
Candidates will design from spec to transistor-level, validate with Cadence tools, and collaborate across AI-enabled design teams to accelerate semiconductor innovation.
Strong background in CMOS, FinFET, and high-frequency IC design, plus scripting in Python or SKILL, is highly valued.