Sr. Analog Design Engineer (TERADYNE, Agoura Hills, CA)

Teradyne; Agoura Hills (CA); On-site; USD 155,000 - 248,000; Full time

Benefits offered by this job

Health benefits

Discretionary bonus plan

Job summary

Teradyne’s Semiconductor Test Division in Agoura Hills, CA is seeking a Senior Analog Design Engineer to design mixed-signal ICs for ATE instruments. You will develop circuit specifications and conceive architectures that meet performance goals across process and operating conditions.

The role requires a BSEE with 8+ years of experience in high-frequency analog/mixed-signal IC design, expertise in VCOs/PLLs/DLLs/ADCs/DACs, and proficiency in Verilog/Verilog-A.

Qualifications

• BSEE required; MSEE or PhD preferred.
• 8+ years of experience in design and characterization of high-frequency mixed-signal ICs.
• Strong knowledge of high-frequency analog mixed-signal design and physical design.
• Experience with VCOs, PLLs, DLLs, ADCs, DACs, clock and data recovery, broadband amplifiers, bias generators, clock distribution networks, high-frequency I/Os, high-frequency CML designs, high voltage.
• Proficiency in Verilog or Verilog-A modeling.
• Cadence Skill or Ocean scripting experience is a plus.
• Experience with ATE test development is a plus.

Responsibilities

• Develop detailed circuit specifications for mixed signal circuits.
• Conceive circuit architectures and transistor-level topologies that satisfy performance.
• Physical implementation (layout) of high speed circuits, directly or with assistance.
• Optimize circuits via simulation with Cadence over process and operating conditions.
• Integration of circuit elements into large analog/mixed-signal ASICs.
• Participation in the characterization of ASIC circuits.

Skills

High-frequency mixed-signal IC design

Verilog/Verilog-A modeling

Mentorship / leading small teams

Layout and physical design

CMOS/BiCMOS knowledge

Education

BSEE

MSEE or PhD in Electrical Engineering

Tools

Cadence EDA tools

Cadence Skill

Ocean scripting

Job description

Select how often (in days) to receive an alert:

Date: Aug 21, 2026

Location: Agoura Hills, CA, US

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together,Teradyne companies deliver manufacturing automation across industries and applications around the world!

We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.

Our Purpose

TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day.

We cultivate a culture of inclusion for all employees that respect their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results.

Opportunity Overview

Teradyne’s Semiconductor Test Division in Agoura Hills, CA is looking for an enthusiastic candidate for the position of Senior Analog Design Engineer, to design low to high-speed circuits in mixed-signal ICs for ATE (Automatic Test Equipment) instruments. We are looking for a candidate with experience in FINFET, general CMOS, and BCD technologies. Responsibilities will include:

• Develop detailed circuit specifications for mixed signal circuits
• Conceive circuit architectures and transistor level circuit topologies that satisfy required performance
• Physical implementation (layout) of high speed circuits, either directly or assisting.
• Optimization of circuits via simulation (with Cadence EDA tools) over all process and operating conditions
• Integration of circuit elements into large analog/mixed signals ASICs
• Participation in the characterization of ASIC circuits.

All About You

We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you’re ready to join us in this mission, take a closer look at the minimum criteria for the position.

• BSEE required. MSEE or PhD in electrical engineering preferred.
• 8+ years of experience in the design and characterization of multiple, high frequency and high scale of integration mixed signal integrated circuits
• Thorough knowledge of high frequency, broad-band Analog Mixed-Signal IC design – both electrical and physical design
• Desire experience in design of VCOs, PLLs, DLLs, ADCs, DACs, clock and data recovery, broadband amplifiers, bias generators, clock distribution networks, high frequency I/Os, high frequency CML designs, high voltage, power circuits
• Solid understanding of CMOS semiconductor device physics and device modeling
• Solid understanding of electromagnetic theory
• Solid understanding of transmission line theory
• Solid understanding of thermal effects of various circuit topologies and different package types
• Involvement in all phases of multiple IC developments from specification to product introduction
• Experience with Cadence Skill or Ocean scripting for automating test benches is a plus
• Proficiency in Verilog or Verilog-A modeling is highly desired
• Mentorship of junior engineers and leader of small development teams
• Generic experience in deep sub-micron CMOS (nodes < 28 nm) highly desired
• Experience in BCD technology is a plus
• Experience with high voltage and/or mixed voltage domain circuit design is desired
• Solid understanding and experience with IC characterization at high frequencies using high speed sampling oscilloscopes, spectrum analyzers, VNAs, signal sources
• Solid understanding of working with PDKs
• Experience with ATE test development is a plus
• Ability to work well with a team

Compensation

The base salary range for this role is $154,900-$247,800. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Incentive Plan

This job is eligible for discretionary bonus(es) based on financial performance.

Benefits

Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more.

Nearest Major Market

Los Angeles

Job Segment

Electrical Engineering, Thermal Engineering, Design Engineer, Manufacturing Engineer, Electrical, Engineering