AI Systems Performance Architect (HW/SW Co-Design)

HP; Palo Alto (CA); In loco; USD 190.000 - 274.000; Tempo pieno

Vantaggi offerti da questo lavoro

Health insurance

Dental insurance

Vision insurance

Disability insurance

Employee assistance program

Flexible spending account

Life insurance

Generous time off

Descrizione del lavoro

HP is seeking a senior engineer to bridge system memory architecture with AI model behavior, optimizing performance via HW/SW co-design and workload tuning. You will drive strategies to reduce memory needs, accelerate startup, and improve inference efficiency while collaborating with stakeholders and leading advanced R&D.

The role involves developing roadmaps for electrical hardware, mentoring teams, and communicating vision to executives and partners across HP.

Competenze

• Requires a Four-year or graduate degree in Electrical Engineering or related field; commensurate experience acceptable.
• Typically 12+ years of experience in electrical design, hardware engineering or related field.

Mansioni

• Analyze system bandwidth, latency, and compute bottlenecks.
• Model performance across CPU/GPU/NPU for AI workloads.
• Simulate workload execution and resource contention.
• Optimize model initialization time, caching, and KV reuse.
• Drive HW/SW co-design for memory, caching, and scheduling.
• Collaborate with ML teams to align model structure with system architecture.
• Define long-term vision and strategy for electrical hardware design across multiple areas.
• Develop technology roadmaps and identify growth opportunities.
• Communicate strategy to executives, partners, and customers.
• Provide innovative solutions and lead cross-disciplinary projects.

Conoscenze

Memory design

AI model design

System architecture

Performance optimization

Debugging

Electrical engineering

Hardware design

MATLAB

Schematic capture

Formazione

Electrical Engineering degree

12+ years experience in relevant field

Strumenti

FPGA

Oscilloscope

CAD tools

Schematic tools

Descrizione del lavoro

HP is seeking a senior engineer to bridge system memory architecture with AI model behavior, optimizing performance via HW/SW co-design and workload tuning. You will drive strategies to reduce memory needs, accelerate startup, and improve inference efficiency while collaborating with stakeholders and leading advanced R&D.

The role involves developing roadmaps for electrical hardware, mentoring teams, and communicating vision to executives and partners across HP.