Memory Architect: AI Hardware & Systems Leader

HP; Houston (TX); On-site; USD 147,000 - 231,000; Full time

Benefits offered by this job

Health insurance

Dental insurance

Vision insurance

Long term disability insurance

Life insurance

Generous paid time off

Job summary

HP Memory Architect is responsible for shaping organization-wide memory architectures and methodologies to reduce memory dependencies in AI PC designs. The role guides tradeoffs, analyzes workloads, and aligns memory technology with HP roadmaps and business value.

It requires senior-level expertise in memory design, FPGA, hardware architecture and collaboration with silicon, firmware, and OS teams to deliver measurable performance improvements and product quality feedback.

Qualifications

• Four-year or graduate degree in Electrical Engineering, or related discipline, or equivalent experience.
• Typically has 10+ years of work experience in electrical design and tools, software, hardware architecture, or related field.

Responsibilities

• Drive memory footprint optimization by analyzing bandwidth, latency, and cache efficiency.
• Model workload sensitivity for AI, graphics, and productivity tasks.
• Partner with silicon, firmware, and OS teams on memory architectures and placements.
• Lead part qualification, quality plans, and manufacturing process qualifications.
• Evaluate new technologies and partnerships for alignment with roadmaps and value.

Skills

Memory design

Computer engineering

Computer science

Debugging

Electrical engineering

Electronic engineering

FPGA

Hardware architecture

Hardware design

MATLAB

New product development

Oscilloscope

Physics

Printed circuit board

Schematic capture

Simulations

Systems design

Education

Electrical Engineering degree

Tools

MATLAB

Oscilloscope

Schematic Capture

Simulations

Job description

HP Memory Architect is responsible for shaping organization-wide memory architectures and methodologies to reduce memory dependencies in AI PC designs. The role guides tradeoffs, analyzes workloads, and aligns memory technology with HP roadmaps and business value.

It requires senior-level expertise in memory design, FPGA, hardware architecture and collaboration with silicon, firmware, and OS teams to deliver measurable performance improvements and product quality feedback.