AI SoC Verification Engineer: UVM & Silicon Debug

Baidu USA; Sunnyvale (CA); On-site; USD 120,000 - 150,000; Full time

Job summary

Baidu USA is seeking an experienced Design Verification Engineer for their Sunnyvale office to verify functionalities of AI SoC. The ideal candidate will have over 5 years of UVM based verification experience, advanced ASIC design knowledge, and solid problem-solving skills.

You will collaborate with cross-functional teams, support mixed-signal co-simulation, and contribute actively to the verification process. Excellent communication skills in both English and Chinese are essential.

Qualifications

• Minimum 5 years of experience of UVM based verification on a significantly complex project.
• Advanced knowledge of standard ASIC design and verification flows.
• Solid verification skills in problem solving and coverage closure.

Responsibilities

• Run RTL and gate level functional verification, debug failures.
• Work closely with design and systems engineering teams.
• Support mixed-signal co-simulation using Verilog models of analog IP.

Skills

UVM based verification

ASIC design and verification flows

System Verilog

Problem solving

Scripting languages (Perl, Python, Tcl)

SoC and IP verification

C/C++

Formal Verification

Excellent communication skills

Job description

Baidu USA is seeking an experienced Design Verification Engineer for their Sunnyvale office to verify functionalities of AI SoC. The ideal candidate will have over 5 years of UVM based verification experience, advanced ASIC design knowledge, and solid problem-solving skills.

You will collaborate with cross-functional teams, support mixed-signal co-simulation, and contribute actively to the verification process. Excellent communication skills in both English and Chinese are essential.