Staff Design Verification Engineer — AI Silicon

Cerebras Systems; Sunnyvale (CA); On-site; USD 250,000 - 300,000; Full time

Job summary

Cerebras Systems in Sunnyvale, CA is seeking an experienced Design Verification engineer to help verify the world\'s largest AI chip. You will design verification strategies and reusable testbenches, ensuring silicon first-pass success across simulation and emulation stages.

Responsibilities include building scalable test environments, debugging complex issues, and collaborating with architecture, RTL, firmware and validation teams.

Qualifications

• Great debugging and problem-solving skills.
• Deep knowledge of SystemVerilog testbench, DPI and UVM.
• Excellent programming skills and knowledge of software engineering practices including object-oriented design.
• Experience developing scalable and portable testbenches and components.
• Experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, and gate level simulations.
• Proficient in scripting languages such as Python or Perl.
• Good interpersonal skills and the ability to work as a standout colleague are a must.
• Extremely self-motivated and eager to solve problems
• 10+ years of Design Verification experience.

Responsibilities

• Work with architects, designers, post silicon and software engineers to ensure a high-quality design that works first silicon.
• Develop and implement verification strategies, detailed tests and coverage plans based on micro-architecture.
• Create verification methodologies and reusable environments, including components such as stimulus, checkers, assertions, and coverage.
• Implement tests, manage regressions, gather coverage, and debug test failures.
• Collaborate with cross-functional teams including architecture, RTL design, physical design, firmware, and validation.
• Analyze and debug complex issues across simulation, emulation, and silicon bring-up phases.
• Continuously enhances verification infrastructure and flows to improve efficiency and quality.
• Contribute to the evolution of the overall verification methodology and best practices across the organization.

Skills

10+ years of DV experience

SystemVerilog

UVM

Python/Perl scripting

Debugging & problem-solving

OO design

Collaboration

Education

BS or MS in Computer Science or Electrical Engineering

Tools

Simulators

Waveform Viewers

Automation/build tools

Job description

Cerebras Systems in Sunnyvale, CA is seeking an experienced Design Verification engineer to help verify the world\'s largest AI chip. You will design verification strategies and reusable testbenches, ensuring silicon first-pass success across simulation and emulation stages.

Responsibilities include building scalable test environments, debugging complex issues, and collaborating with architecture, RTL, firmware and validation teams.