AI-Powered Power Analytics Engineer (EDA)

3M HEALTHCARE; Santa Clara (CA); On-site; USD 136,000 - 264,500; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a Power/Architectural Engineer in Santa Clara to analyze full-chip and unit-level power, developing power-aware models and flows, and training LLMs for power analysis. You will translate power data into concrete design improvements and collaborate across Architects, ASIC Design, and Physical Design teams.

The role involves designing in Verilog, automating workflows with Python/Perl/C++, and exploring ML/RL approaches for anomaly detection and optimization.

Qualifications

• MS (or equivalent) plus 5 years of relevant experience, or PhD plus 3 years in EE/CE/CS
• Strong understanding of energy consumption, power estimation, data movement and low-power design
• Hands-on experience with Verilog and ASIC design principles; familiarity with RTL/gate-level tools
• Proficient coding in Python, Perl, and C++
• Experience or interest in ML/RL and data analytics applied to EDA/architecture
• Interest in building and using LLMs as engineering copilots for EDA/power workflows

Responsibilities

• Analyze full-chip and unit-level power using RTL and gate-level tools and translate data into design improvements
• Develop power-aware models and flows, including ML/RL techniques for anomaly detection and power management
• Design and train new LLMs that learn power analysis from design data and reports to assist engineers
• Perform comparative power analysis across workloads to identify optimization opportunities
• Collaborate with Architects, Performance, Software, ASIC Design, and Physical Design to drive fixes
• Prototype and evaluate new architectural features in Verilog with power implications
• Automate and scale flows (Python/Perl/C++) and close the loop between power data, AI models, and design decisions
• Apply AI to power optimization to suggest or tune power-efficient configurations

Skills

Power analysis

Verilog

Python

C++

ML/RL

Data analytics

Cross-functional teamwork

Education

MS or equivalent + 5 yrs

PhD + 3 yrs

Tools

PowerArtist

PrimePower RTL

RTL Architect

Job description

NVIDIA is seeking a Power/Architectural Engineer in Santa Clara to analyze full-chip and unit-level power, developing power-aware models and flows, and training LLMs for power analysis. You will translate power data into concrete design improvements and collaborate across Architects, ASIC Design, and Physical Design teams.

The role involves designing in Verilog, automating workflows with Python/Perl/C++, and exploring ML/RL approaches for anomaly detection and optimization.