Senior Power Analysis and Optimization Engineer

3M HEALTHCARE; Santa Clara (CA); On-site; USD 136,000 - 264,500; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a Power/Architectural Engineer in Santa Clara to analyze full-chip and unit-level power, developing power-aware models and flows, and training LLMs for power analysis. You will translate power data into concrete design improvements and collaborate across Architects, ASIC Design, and Physical Design teams.

The role involves designing in Verilog, automating workflows with Python/Perl/C++, and exploring ML/RL approaches for anomaly detection and optimization.

Qualifications

• MS (or equivalent) plus 5 years of relevant experience, or PhD plus 3 years in EE/CE/CS
• Strong understanding of energy consumption, power estimation, data movement and low-power design
• Hands-on experience with Verilog and ASIC design principles; familiarity with RTL/gate-level tools
• Proficient coding in Python, Perl, and C++
• Experience or interest in ML/RL and data analytics applied to EDA/architecture
• Interest in building and using LLMs as engineering copilots for EDA/power workflows

Responsibilities

• Analyze full-chip and unit-level power using RTL and gate-level tools and translate data into design improvements
• Develop power-aware models and flows, including ML/RL techniques for anomaly detection and power management
• Design and train new LLMs that learn power analysis from design data and reports to assist engineers
• Perform comparative power analysis across workloads to identify optimization opportunities
• Collaborate with Architects, Performance, Software, ASIC Design, and Physical Design to drive fixes
• Prototype and evaluate new architectural features in Verilog with power implications
• Automate and scale flows (Python/Perl/C++) and close the loop between power data, AI models, and design decisions
• Apply AI to power optimization to suggest or tune power-efficient configurations

Skills

Power analysis

Verilog

Python

C++

ML/RL

Data analytics

Cross-functional teamwork

Education

MS or equivalent + 5 yrs

PhD + 3 yrs

Tools

PowerArtist

PrimePower RTL

RTL Architect

Job description

What You’ll Be Doing:

• Analyze full‑chip and unit‑level power using internal and industry‑standard RTL and gate‑level power tools, and translate data into concrete design and architectural improvements.
• Develop and productionize power‑aware models and flows, including ML/RL‑based techniques for anomaly detection, dynamic power management, and design‑space exploration.
• Design and train new LLMs that “learn the art” of power analysis from design data, power reports, bug histories, and best practices—so they can:
  • Assist engineers in interpreting complex power data
  • Propose likely root causes and candidate fixes
  • Recommend architectural and micro‑architectural optimizations for power
• Perform comparative power analysis across workloads, products, and design options to identify trends, anomalies, and optimization opportunities that aren’t obvious from first principles alone.
• Partner closely with Architects, Performance, Software, ASIC Design, and Physical Design teams to interpret power data, root‑cause power bugs, and drive fixes and design changes.
• Prototype and evaluate new architectural features in Verilog, with a strong focus on their power and energy implications.
• Automate and scale flows (Python/Perl/C++) and define new pipelines that fast‑track power anomaly detection and close the loop between power data, AI models, and design decisions.
• Apply AI to power optimization: build and deploy data‑driven models—using machine learning, reinforcement learning, data analytics, and custom LLMs—to recommend or automatically tune power‑efficient configurations and policies.

What We Need To See:

• MS (or equivalent experience) and 5yrs experience OR PhD + 3yr experience in EE/CE/CS or related fields.
• Strong understanding of energy consumption, power estimation, data movement, and low‑power design.
• Familiarity with Verilog and ASIC design principles, and hands‑on experience with tools such as PowerArtist, PrimePower/PrimePower RTL, RTL Architect, or similar.
• Solid coding and automation skills, preferably in Python, Perl, and C++.
• Experience or strong interest in machine learning, reinforcement learning, and data analytics, ideally applied to EDA, architecture, or system‑level optimization.
• Interest or experience in building and using LLMs or other foundation models as engineering copilots—especially for EDA/power/architecture workflows.
• Excellent communication and collaboration skills to work effectively with cross‑functional design and architecture teams.
• A genuine desire to bring data‑driven, AI‑assisted decision‑making into power architecture and help shape the energy profile of NVIDIA’s future products.

Benefits and Compensation

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is $136,000 USD - $218,500 USD for Level 3, and $168,000 USD - $264,500 USD for Level 4.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until May 12, 2026.

This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering a diverse work environment and is proud to be an equal opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law.