Senior Power Methodology and Modeling Engineer

NVIDIA; Santa Clara (CA); On-site; USD 130,000 - 160,000; Full time

Job summary

NVIDIA is seeking a member of the Architecture Energy Modeling Team in Santa Clara to collaborate on energy modeling for next-gen GPUs and CPUs. This role includes defining tools for data generation, improving power efficiency through data analysis, and experimenting with machine learning techniques. A Master's or PhD with 5+ years of experience is required, along with strong coding skills in Python and C++. Join us to enhance our understanding of energy usage in graphics and AI workloads.

Qualifications

• 5+ years of experience in a relevant field.
• Strong background of VLSI, digital design, and computer architecture concepts.
• Basic understanding of chip design process from RTL design to tape-out.

Responsibilities

• Define and implement tools for data generation for power analytical model.
• Develop tools to sanitize metrics in the model for accuracy.
• Integrate power models with performance tools.
• Mine data to find important data paths and improve power efficiency.

Skills

Strong coding skills, preferably in Python

Strong coding skills, preferably in C++

Ability to formulate and analyze algorithms

Good understanding of power and energy concepts

Strong background in VLSI and computer architecture

Background in machine learning and statistical modeling

Education

MS or PhD in related fields

Job description

Overview

As a member of the Architecture Energy Modeling Team, you will collaborate with Architects, ASIC Design Engineers, Low Power Engineers, Performance Engineers, Software Engineers, and Physical Design teams to study and implement energy modeling techniques for NVIDIA's next generation GPUs, CPUs and Tegra SOCs. Your contributions will help us understand energy usage in graphics and AI workloads and make improvements in architecture, design, and power management.

Responsibilities

• Define and implement tools and methodologies for efficient data generation from post layout netlists to feed into data movement power analytical model.
• Develop tools and infrastructure to sanitize each metric in the model to achieve high correlation accuracy.
• Define and implement tools and methodologies for efficient integration of power models with performance tools.
• Identify runtime and memory limitation of existing flows and tools to speedup model delivery process.
• Mine data from pre- and post-silicon performance runs to find important data paths and bottlenecks. Give feedback to design teams and improve power efficiency.
• Work with floorplan, performance, verification and emulation methodology and infrastructure development teams to integrate data movement power models.
• Experiment with various ML techniques to answer what-if design questions and set proper power/energy targets for next generation chips.
• Enable efficient storage and retrieval of data from database.
• Enable easy visualization of data using platforms such as PowerBI, OpenSearch.

Qualifications

• MS (or equivalent experience) with proven experience or PhD in related fields
• 5+ years of experience
• Strong coding skills, preferably in Python, C++.
• Ability to formulate and analyze algorithms, and comment on their runtime and memory complexities.
• Strong background of VLSI, digital design, and computer architecture concepts.
• Good understanding of fundamental concepts of power and energy consumption, estimation, and low power design.
• Basic understanding of chip design process from RTL design to tape-out.
• Background in machine learning, AI, and/or statistical modeling is a plus.
• Desire to bring quantitative decision-making and analytics to improve the energy efficiency of our products.