Senior Power Analysis and Optimization Engineer

NVIDIA; Santa Clara (CA); On-site; USD 136,000 - 265,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a Senior Power Architecture & Optimization Engineer to push energy efficiency using AI, ML, and LLMs tailored for power analysis. You will shape power models for full-chip and unit designs, and collaborate across architecture, ASIC, and physical design teams.

You’ll develop power-aware methodologies, train LLMs on design data, and automate flows to accelerate power optimization. Strong Verilog/RTL experience and Python/C++ automation are essential.

Qualifications

• MS in EE/CE/CS with 5 years’ industry experience or PhD with 3 years’ experience.
• Strong knowledge of energy consumption and low‑power design.
• Hands‑on Verilog/ASIC design experience with relevant tools.
• Proficient in Python, Perl, and C++ for automation.

Responsibilities

• Analyze full‑chip and unit‑level power data to drive architectural improvements.
• Develop and productionize power‑aware models and flows using ML/RL techniques.
• Design and train LLMs to learn power analysis from design data and reports.
• Automate flows and build pipelines to speed up power anomaly detection.

Skills

Python

Perl

C++

Verilog

Machine learning

Data analytics

Education

MS in EE/CE/CS

PhD in EE/CE/CS

Tools

PowerArtist

PrimePower RTL

RTL Architect

Job description

We’re looking for a Senior Power Architecture & Optimization Engineer to push the limits of energy efficiency using advanced analytics and AI, including LLMs trained specifically for power analysis.

NVIDIA’s leadership in accelerated computing depends on building the most energy‑efficient GPUs and SoCs in the industry. As AI and graphics workloads scale explosively, we believe that Power Analysis and Optimization driven by AI and LLMs is the future—and a key differentiator for our next generations of GPUs and Tegra SoCs. In this role, you’ll be at the center of that effort—combining power architecture expertise with machine learning, reinforcement learning, data analytics, and large language models (LLMs) to invent new ways to model, analyze, and optimize energy consumption across full‑chip and unit‑level designs.

What You’ll Be Doing

• Analyze full‑chip and unit‑level power using internal and industry‑standard RTL and gate‑level power tools, and translate data into concrete design and architectural improvements.
• Develop and productionize power‑aware models and flows, including ML/RL‑based techniques for anomaly detection, dynamic power management, and design‑space exploration.
• Design and train new LLMs that “learn the art” of power analysis from design data, power reports, bug histories, and best practices—so they can:
• Assist engineers in interpreting complex power data
• Propose likely root causes and candidate fixes
• Recommend architectural and micro‑architectural optimizations for power
• Perform comparative power analysis across workloads, products, and design options to identify trends, anomalies, and optimization opportunities that aren’t obvious from first principles alone.
• Partner closely with Architects, Performance, Software, ASIC Design, and Physical Design teams to interpret power data, root‑cause power bugs, and drive fixes and design changes.
• Prototype and evaluate new architectural features in Verilog, with a strong focus on their power and energy implications.
• Automate and scale flows (Python/Perl/C++) and define new pipelines that fast‑track power anomaly detection and close the loop between power data, AI models, and design decisions.
• Apply AI to power optimization: build and deploy data‑driven models—using machine learning, reinforcement learning, data analytics, and custom LLMs—to recommend or automatically tune power‑efficient configurations and policies.

What We Need To See

• MS (or equivalent experience) and 5yrs experience OR PhD + 3yr experience in EE/CE/CS or related fields.
• Strong understanding of energy consumption, power estimation, data movement, and low‑power design.
• Familiarity with Verilog and ASIC design principles, and hands‑on experience with tools such as PowerArtist, PrimePower/PrimePower RTL, RTL Architect, or similar.
• Solid coding and automation skills, preferably in Python, Perl, and C++.
• Experience or strong interest in machine learning, reinforcement learning, and data analytics, ideally applied to EDA, architecture, or system‑level optimization.
• Interest or experience in building and using LLMs or other foundation models as engineering copilots—especially for EDA/power/architecture workflows.
• Excellent communication and collaboration skills to work effectively with cross‑functional design and architecture teams.
• A genuine desire to bring data‑driven, AI‑assisted decision‑making into power architecture and help shape the energy profile of NVIDIA’s future products.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until May 26, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

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