AI-Optimized Memory Microarchitecture Engineer

Micron Technology, Inc.; Folsom (CA); On-site; USD 177,000 - 309,000; Full time

Benefits offered by this job

Medical/Dental/Vision plans

Paid time off

Paid holidays

Job summary

Micron Technology, Inc. in the United States is seeking a Member of Technical Staff to advance AI-ready memory architectures. You will translate architecture concepts into silicon, focusing on performance, power, area, and reliability while collaborating with design and verification teams.

Join our AI-optimized Architecture team to design high‑performance memory for AI workloads, review SystemVerilog designs, perform early analysis, and help shape microarchitecture from concept to implementation.

Qualifications

• Strong experience in digital design and microarchitecture development.
• Solid understanding of computer and memory system architecture with ability to reason about SoC-level behavior.
• Experience with synthesis, and early PPA estimation and optimization.
• Experience in C/C++ and Python and SystemVerilog.
• Ability to influence others through data-driven analysis.

Responsibilities

• Translate architecture requirements into efficient, scalable microarchitectures
• Design, implement, and review SystemVerilog designs for memory systems architectures
• Perform synthesis and early analysis to optimize area, power, and timing
• Compose and maintain microarchitecture documentation
• Drive technical decisions by evaluating tradeoffs across constraints

Skills

Digital design

Microarchitecture

RTL design

SystemVerilog

C/C++

Python

Education

Master's or PhD in Computer Science / Computer Engineering / Electrical Engineering

Tools

Synthesis tools

Job description

Micron Technology, Inc. in the United States is seeking a Member of Technical Staff to advance AI-ready memory architectures. You will translate architecture concepts into silicon, focusing on performance, power, area, and reliability while collaborating with design and verification teams.

Join our AI-optimized Architecture team to design high‑performance memory for AI workloads, review SystemVerilog designs, perform early analysis, and help shape microarchitecture from concept to implementation.