AI-Optimized Memory Design Engineer

1000 Micron Technology, Inc.; Folsom (CA); On-site; USD 175,000 - 309,000; Full time

Benefits offered by this job

Medical plans

Dental plans

Vision plans

Paid time off

Equity opportunities

Job summary

Micron Technology, Inc. is seeking a Member of Technical Staff to translate architectural vision into efficient silicon-proven hardware for AI-optimized memory systems. You will work on tightly coupled, high-performance memory architectures balancing performance, power, area and reliability.

The role emphasizes ownership of hardware blocks, SystemVerilog RTL design, and collaboration across teams to guide design decisions across the development lifecycle.

Qualifications

• Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering, or related field.
• Strong digital design and microarchitecture development with ownership of hardware blocks.
• Solid understanding of computer architecture and memory systems, including SoC behaviors.
• Experience with synthesis flows and early PPA estimation and optimization.
• Proficiency in SystemVerilog and at least one language such as C, C++, or Python.

Responsibilities

• Translate architecture requirements into scalable microarchitectures and drive implementation from concept through silicon.
• Design, implement, and review SystemVerilog RTL for advanced memory system architectures.
• Perform synthesis and early PPA analysis to optimize area, power, and timing.
• Develop and maintain microarchitecture documentation aligning design intent across teams.
• Evaluate architectural and implementation tradeoffs to support technical decision-making.

Skills

Digital design

SystemVerilog

C/C++/Python

Memory systems

Education

Bachelor's in CS/CE/EE

Job description

Micron Technology, Inc. is seeking a Member of Technical Staff to translate architectural vision into efficient silicon-proven hardware for AI-optimized memory systems. You will work on tightly coupled, high-performance memory architectures balancing performance, power, area and reliability.

The role emphasizes ownership of hardware blocks, SystemVerilog RTL design, and collaboration across teams to guide design decisions across the development lifecycle.