Member of Technical Staff, AI‑Optimized Memory Digital Design Engineer / Microarchitect

Micron Technology, Inc; Folsom (CA); On-site; USD 120,000 - 150,000; Full time

Job summary

Micron Technology, Inc is seeking a Member of Technical Staff for AI-Optimized Memory Digital Design in Folsom, California. This role will focus on designing high-performance memory solutions tailored for artificial intelligence applications.

The ideal candidate will have 5+ years of digital design experience, a Master's or PhD in related fields, and solid knowledge in microarchitecture and memory systems, providing a unique opportunity to influence next-generation technology.

Qualifications

• 5+ years of proven industry experience delivering silicon‑demonstrated memory systems.
• Solid understanding of computer and memory system architecture.
• Familiarity with memory interfaces and their concepts.

Responsibilities

• Translate architecture requirements into scalable microarchitectures.
• Design and implement SystemVerilog designs for memory systems.
• Perform synthesis and early analysis for PPA optimization.

Skills

Digital design experience

Microarchitecture development

High-level programming (C/C++, Python)

Hardware description (SystemVerilog)

Education

Masters or PhD in Computer Science or related field

Job description

Req ID: JR94197 Member of Technical Staff, AI‑Optimized Memory Digital Design Engineer / Microarchitect

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Interested in changing the landscape of artificial intelligence workloads? Join our team where we are building next‑generation, high‑performance memory solutions for AI. In Micron's AI‑optimized Memory Architecture organization, we partner closely with customers to design and deliver memory solutions purpose‑built for emerging AI systems and applications.

As a Member of Technical Staff in the AI‑optimized Architecture team, you will contribute to the microarchitecture and design of tightly coupled, high‑performance memory for AI. Apply expert knowledge to realize architecture features into silicon, with a strong focus on performance, power, area, (PPA) and reliability. This role is ideal for an engineer who combines deep digital design experience with strong architecture intuition, motivated by turning architectural intent into efficient, silicon‑proven implementations!

Job Responsibilities:

• Translate architecture requirements into efficient, scalable microarchitectures that optimize systems metrics with ownership from concept through implementation.
• Design, implement, and review SystemVerilog designs for memory systems architectures.
• Perform synthesis and early analysis to estimate and optimize area, power, and timing, and to guide architecture and microarchitecture tradeoffs.
• Compose and maintain clear microarchitecture documentation that aligns design intent across teams.
• Drive technical decisions by evaluating tradeoffs across microarchitecture and implementation constraints.

Preferred Qualifications:

• Strong experience in digital design and microarchitecture development, including ownership of hardware blocks from specification through implementation.
• Solid understanding of computer and memory system architecture with an ability to reason about SoC‑level behavior and tradeoffs.
• Experience with synthesis, and early PPA estimation and optimization.
• Experience in one or more high‑level programming languages (e.g., C/C++, Python) and hardware description languages (e.g., SystemVerilog).
• Ability to influence others through deeply technical, data‑driven analysis.

Minimum Qualifications:

• Familiarity with memory interfaces and memory systems concepts (reliability, media management, etc.).
• Experience connecting architecture and implementation by influencing architecture features with a clear understanding of RTL cost and feasibility.
• A Masters or PhD in Computer Science, Computer Engineering, Electrical Engineering, or equivalent experience.
• 5+ years of proven industry experience delivering silicon‑demonstrated memory systems and SoC hardware designs on modern foundry nodes.

Job Profile(s):

Systems Design Engineering MTS

Relocation Level:

TBD

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.