Infrastructure AI/ML Engineer for Memory Design, Characterization, and Yield Optimization

Frontdoor Defense; Austin (TX); On-site; USD 151,000 - 241,000; Full time

Benefits offered by this job

Discretionary bonus

Equity grants

Medical, dental, vision plans

401(k) with company match

Employee Stock Purchase Program (ESPP)

Job summary

Broadcom in Austin, Texas is seeking an Infrastructure AI/ML Engineer to lead Agentic AI workflows for memory design, characterization, and yield optimization. You will partner with memory designers and DFT experts to drive state-of-the-art embedded memory development optimized for PPA and yield.

The role requires 15+ years in memory design/DFT and AI systems engineering, with a Master’s or PhD in Electrical/Computer Engineering.

Qualifications

• 15+ years of progressive, relevant experience in Memory design, DFT, Silicon Yield Analysis, software architecture and AI systems engineering.
• Master's degree or Ph.D. in Electrical Engineering or Computer Engineering.

Responsibilities

• Conceptualize, architect, deploy, and scale robust, distributed multi-agent AI frameworks for memory design and yield optimization.
• Orchestrate autonomous agent executions across memory design development, silicon bring-up, and yield analysis.
• Integrate LLM-driven agent pipelines with EDA tools, internal software and data repositories.
• AI-driven debug: classify scan failures and correlate with DFT structures.
• Predictive yield modeling using Fab params, PCM and E-test data to foresee yield excursions.
• Collaborate with Memory Design Leads, EDA Tool Specialists, and Infra Engineers to create modular workflows.
• Align AI workflow capabilities with efficiency targets and milestones.

Skills

Embedded memory design

Compute-in-memory

LLM apps

Multi-agent orchestration

Function-calling

RAG (retrieval-augmented generation)

LangGraph

Chip design methodologies

IP block lifecycles

Verification environments

Python

TCL

Microservices

REST APIs

Docker

Kubernetes

Sandboxing

Workflow orchestration

Evaluation metrics

Testing benchmarks

Safety guardrails

Vector databases

Cloud-native orchestration

Education

Master's degree in Electrical Engineering or Computer Engineering

Ph.D. in Electrical Engineering or Computer Engineering

Tools

Synopsys

Cadence

Siemens EDA

SystemVerilog

UVM

Job description

Infrastructure AI/ML Engineer for Memory Design, Characterization, and Yield Optimization

Lead development of an Agentic AI infrastructure to optimize memory design and yield

Location: Austin, Texas

Compensation: $150,800 - 241,200 USD / year

About The Role

Infrastructure AI/ML Engineer

The Central Engineering Group is seeking an energetic, visionary, and passionate Infrastructure AI/ML Engineer to lead the Agentic AI Infrastructure development workflow for memory design, characterization, and yield optimization.

In this role, you will collaborate with memory designers and DFT experts to build Agentic AI workflows that drive the development of state-of-the-art embedded memories optimized for PPA, DFT, and yield.

Minimum Education & Experience Qualifications

Experience: 15+ years of progressive, relevant experience in Memory design, DFT, Silicon Yield Analysis, software architecture and AI systems engineering.

Education: Master's degree or Ph.D. in Electrical Engineering or Computer Engineering.

Key Job Responsibilities

• Conceptualize, architect, deploy, and scale robust, distributed multi-agent AI frameworks tailored to transform intricate memory design workflows optimized for performance, power, area, and yield.
• Orchestrate long-horizon, autonomous agent executions capable of managing multi-step reasoning, task decomposition, and decision-making across all phases of memory design development, silicon bring-up, and yield analysis.
• Seamlessly integrate Large Language Model (LLM)-driven agent pipelines with core Electronic Design Automation (EDA) suites, custom in-house software tools, and enterprise data repositories.
• AI-Driven Debug: Develop and deploy ML models to automate the classification of scan failures (Chain, Stuck-at, Transition) and correlate them with design-for-test (DFT) structures.
• Predictive Yield Modeling: Integrate high-dimensional data—including Fab process parameters, PCM (Process Control Monitoring), and E-test data—to predict yield excursions before they hit the assembly line.
• Partner collaboratively with Memory Design Leads, EDA Tool Specialists, and Infrastructure Engineers to distill complex, domain-specific hardware engineering methodologies into modular, goal-driven agentic workflows.
• Align AI workflow capabilities directly with organizational efficiency targets and technical milestones across the Central Engineering Group.

Required Skillset & Technical Competencies

Memory Design, Characterization and Yield Analysis

• Experience designing and characterizing embedded memory in advanced technology process nodes
• Experience in compute-in-memory design and architecture

AI Engineering & Multi-Agent Expertise

• Experience architecting production-grade LLM applications: multi-agent orchestration, function-calling/tool-use, and retrieval-augmented generation (RAG).
• Experience integrating agentic systems with enterprise tools, services, and knowledge sources – including building and consuming Model Context Protocol (MCP) servers, and packaging reusable agent capabilities (e.g., Agent Skills).
• Deep experience with agent orchestration frameworks such as LangGraph.

Semiconductor Domain Knowledge & EDA Tooling

• Fundamental grasp of chip design methodologies, IP block development lifecycles, and verification environments.
• Hands-on familiarity with industry-standard EDA tooling and frameworks from Synopsys, Cadence, and Siemens EDA, alongside System Verilog & UVM verification environments.

Software Engineering & Infrastructure Mastery

• High proficiency in core programming languages and system design concepts, specifically Python and TCL.
• Expertise in microservices architecture, REST APIs, Docker, Kubernetes, Sandboxing, and config-driven workflow orchestration engine design.

AI System Verification & Data Engineering

• Proven experience establishing evaluation metrics, testing benchmarks, and safety guardrails for non-deterministic AI systems in high-stakes environments.
• Technical depth in Vector Databases, and cloud-native containerized orchestration pipelines.

Compensation and Benefits

The annual base salary range for this position is USD 150,800.00 To USD 241,200.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.